公开(公告)号：US20100109756A1

公开(公告)日：2010-05-06

申请号：US12686430

申请日：2010-01-13

申请人： Hiroaki NAKAYA ,  Satoru AKIYAMA ,  Tomonori SEKIGUCHI ,  Riichiro TAKEMURA

发明人： Hiroaki NAKAYA ,  Satoru AKIYAMA ,  Tomonori SEKIGUCHI ,  Riichiro TAKEMURA

IPC分类号： G05F1/10

CPC分类号： G11C5/146 ,  G11C11/401 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate voltage control technique that prevents the operating speed from being decreased and suppresses a leakage current due to a lower threshold voltage with respect to a low voltage use. Since a center value of the threshold voltages is detected by plural replica MOS transistors, and a substrate voltage is controlled to control a center value of the threshold voltages, thereby making it possible to satisfy a lower limit of the operating speed and an upper limit of a leakage current of the entire chip. On the other hand, the substrate voltage is dynamically controlled during the operation of the chip, thereby making it possible to decrease the center value of the threshold voltages when the chip operates to improve the speed, and to increase the center value of the threshold voltages after the operation of the chip to reduce the leakage current of the entire chip.

摘要翻译： 一种防止工作速度降低的基板电压控制技术，并且相对于低电压使用而抑制由于阈值电压较低导致的漏电流。 由于通过多个复制MOS晶体管检测阈值电压的中心值，并且控制衬底电压以控制阈值电压的中心值，从而可以满足操作速度的下限和上限 整个芯片的漏电流。 另一方面，在芯片工作期间动态地控制衬底电压，从而可以在芯片工作时降低阈值电压的中心值以提高速度，并且增加阈值电压的中心值 芯片运行后降低整个芯片的漏电流。

公开(公告)号：US20090066390A1

公开(公告)日：2009-03-12

申请号：US12205668

申请日：2008-09-05

申请人： Akira IDE ,  Yasuhiro TAKAI ,  Tomonori SEKIGUCHI ,  Riichiro TAKEMURA ,  Satoru AKIYAMA ,  Hiroaki NAKAYA

发明人： Akira IDE ,  Yasuhiro TAKAI ,  Tomonori SEKIGUCHI ,  Riichiro TAKEMURA ,  Satoru AKIYAMA ,  Hiroaki NAKAYA

IPC分类号： H03H11/26

CPC分类号： H03K5/15033

摘要： Disclosed is a timing control circuit which receives a first clock having a period T1 and a group of second clocks of L different phases (where L is a positive integer) spaced apart from each other at substantially equal intervals and which generates a fine timing signal delayed from the rising edge of the first clock by a delay td of approximately td=m·T1+n·(T2/L), where m and n are non-negative integers. The timing control circuit has a coarse delay circuit and a fine delay circuit. The coarse delay circuit counts the rising edges of the first clock after an activate signal is activated and generates a coarse timing signal delayed from the first clock by approximately m·T1. The fine delay circuit has a circuit which, after the activate signal is activated, detects a second clock, which has a rising edge that immediately follows the rising edge of the first clock, from among the group of L-phase second clocks. Using the edge-detection information, the fine delay circuit generates a fine timing signal for which the amount of delay from the coarse timing signal is approximately n·(T2/L). The values of m and n can be set by registers.

摘要翻译： 公开了一种定时控制电路，其以基本相等的间隔接收具有周期T1和L个不同相位（其中L是正整数）的第二时钟的一组第一时钟，并且产生延迟的精细定时信号 从第一时钟的上升沿开始约td = m.T1 + n。（T2 / L）的延迟td，其中m和n是非负整数。 定时控制电路具有粗略延迟电路和精细延迟电路。 粗略延迟电路在激活信号激活后对第一时钟的上升沿进行计数，并产生从第一个时钟延迟大约m.T1的粗略定时信号。 精细延迟电路具有在激活信号被激活之后，从一组L相第二时钟中检测出具有紧跟第一时钟的上升沿的上升沿的第二时钟的电路。 利用边缘检测信息，精细延迟电路产生从粗定时信号的延迟量近似为n的精细定时信号（T2 / L）。 m和n的值可以由寄存器设置。

公开(公告)号：US20180254400A1

公开(公告)日：2018-09-06

申请号：US15757229

申请日：2016-08-30

申请人： Hiroaki NAKAYA

发明人： Hiroaki NAKAYA

IPC分类号： H01L35/22 ,  C01B32/168 ,  C01B32/21 ,  H01L35/16 ,  H01L35/24 ,  H01L35/32

CPC分类号： H01L35/22 ,  C01B32/168 ,  C01B32/21 ,  H01L35/16 ,  H01L35/24 ,  H01L35/32

摘要： The present invention provides thermoelectric conversion elements and thermoelectric conversion modules which are possible to effectively use oxide materials having high Seebeck coefficient, and excellently improve their outputs. The present invention provides thermoelectric conversion elements which comprise at least a charge transport layer, thermoelectric conversion material layers and electrodes, wherein the charge transport layer comprises a graphite treated to dope charge-donating materials so that the graphite has an n-type semiconductor property, or a graphite treated to dope charge-accepting materials so that the graphite has a p-type semiconductor property, and provides thermoelectric conversion modules using the thermoelectric conversion elements.

公开(公告)号：US20110158676A1

公开(公告)日：2011-06-30

申请号：US12955632

申请日：2010-11-29

申请人： Hiroaki NAKAYA ,  Takafumi NAGAI

发明人： Hiroaki NAKAYA ,  Takafumi NAGAI

IPC分类号： G03G21/20

CPC分类号： G03G21/20 ,  G03G2221/1678

摘要： An image forming apparatus includes a fusing device; a developing device; a partition wall disposed between the fusing device and the developing device, wherein the partition wall includes a Peltier element for transferring heat from the developing device to the fusing device and a cooling heat storage member disposed nearer to the developing device than the Peltier element.

摘要翻译： 一种图像形成装置，包括定影装置; 显影装置; 分隔壁，其设置在定影装置和显影装置之间，其中分隔壁包括用于将热量从显影装置传送到定影装置的珀耳帖元件和布置成比珀耳帖元件更靠近显影装置的冷却储热构件。

公开(公告)号：US20200006615A1

公开(公告)日：2020-01-02

申请号：US16490700

申请日：2018-02-28

申请人： Hiroaki NAKAYA

发明人： Hiroaki NAKAYA

IPC分类号： H01L35/30 ,  H01L35/32

摘要： The present invention provides a thermoelectric conversion module which can utilize sunlight and solar heat by using high output charge-transport-type thermoelectric conversion elements. The present invention provides A thermoelectric conversion module which comprises at least a thermoelectric conversion module-element in which charge-transport-type thermoelectric conversion elements are formed and a photothermal conversion substrate containing photothermal conversion material, wherein the thermoelectric conversion module-element comprises an insulating substrate, and n-type and/or p-type charge-transport-type thermoelectric conversion elements are formed on the insulating substrate, wherein the charge-transport-type thermoelectric conversion element comprises a charge transport layer and thermoelectric conversion material layers and electrodes, wherein the photothermal conversion substrate is disposed so that it absorbs external light and converts it into heat and transfers the heat to the electrodes or the thermoelectric conversion material layers disposed on the charge transport layers.

公开(公告)号：US20110107064A1

公开(公告)日：2011-05-05

申请号：US12915158

申请日：2010-10-29

申请人： Hiroaki NAKAYA ,  Yuki Kondoh ,  Makoto Ishikawa

发明人： Hiroaki NAKAYA ,  Yuki Kondoh ,  Makoto Ishikawa

IPC分类号： G06F9/30

CPC分类号： G06F9/382 ,  G06F9/30149 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/3802 ,  G06F9/3822

摘要： The present invention realizes an efficient superscalar instruction issue and low power consumption at an instruction set including instructions with prefixes. An instruction fetch unit is adopted which determines whether an instruction code is of a prefix code or an instruction code other than it, and outputs the result of determination and the 16-bit instruction code. Along with it, decoders each of which decodes the instruction code, based on the result of determination, and decoders each of which decodes the prefix code, are disposed separately. Further, a prefix is supplied to each decoder prior to a fixed-length instruction code like 16 bits modified with it. A fixed-length instruction code following the prefix code is supplied to each decoder of the same pipeline as the decoder for the prefix code.

摘要翻译： 本发明在包括具有前缀的指令的指令集上实现有效的超标量指令问题和低功耗。 采用指令取出单元，其判定指令码是否是前缀码，也可以是除了指令码以外的指令码，并输出确定结果和16位指令码。 与此同时，基于确定结果解码指令代码的解码器和分别解码前缀码的解码器分别设置。 此外，在固定长度指令代码（如16位修改）之前，将前缀提供给每个解码器。 与前缀码相邻的固定长度指令代码被提供给与前缀码的解码器相同的流水线的每个解码器。