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    Timing control circuit and semiconductor storage device
    3.
    发明授权
    Timing control circuit and semiconductor storage device 有权
    定时控制电路和半导体存储设备

    公开(公告)号：US07973582B2

    公开(公告)日：2011-07-05

    申请号：US12205668

    申请日：2008-09-05

    Applicant: Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

    Inventor： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

    IPC: H03H11/26

    CPC classification number: H03K5/15033

    Abstract: Disclosed is a timing control circuit which receives a first clock having a period T1 and a group of second clocks of L different phases (where L is a positive integer) spaced apart from each other at substantially equal intervals and which generates a fine timing signal delayed from the rising edge of the first clock by a delay td of approximately td=m·T1+n·(T2/L), where m and n are non-negative integers. The timing control circuit has a coarse delay circuit and a fine delay circuit. The coarse delay circuit counts the rising edges of the first clock after an activate signal is activated and generates a coarse timing signal delayed from the first clock by approximately m·T1. The fine delay circuit has a circuit which, after the activate signal is activated, detects a second clock, which has a rising edge that immediately follows the rising edge of the first clock, from among the group of L-phase second clocks. Using the edge-detection information, the fine delay circuit generates a fine timing signal for which the amount of delay from the coarse timing signal is approximately n·(T2/L). The values of m and n can be set by registers.

    Abstract translation: 公开了一种定时控制电路，其以基本相等的间隔接收具有周期T1和L个不同相位（其中L是正整数）的第二时钟的一组第一时钟，并且产生延迟的精细定时信号 从第一时钟的上升沿开始约td = m·T1 + n·（T2 / L）的延迟td，其中m和n是非负整数。 定时控制电路具有粗略延迟电路和精细延迟电路。 粗略延迟电路在激活信号激活后对第一时钟的上升沿进行计数，并产生从第一个时钟延迟大约m·T1的粗略定时信号。 精细延迟电路具有在激活信号被激活之后，从一组L相第二时钟中检测出具有紧跟第一时钟的上升沿的上升沿的第二时钟的电路。 利用边缘检测信息，精细延迟电路产生从粗定时信号的延迟量近似为n·（T2 / L）的精细定时信号。 m和n的值可以由寄存器设置。

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07903492B2

    公开(公告)日：2011-03-08

    申请号：US12314860

    申请日：2008-12-17

    Applicant: Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

    Inventor： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

    IPC: G11C7/00

    CPC classification number: G11C7/22 ,  G11C7/04 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/20 ,  G11C7/222 ,  G11C11/4094 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10897 ,  H03K5/15066

    Abstract: Disclosed is a semiconductor device including a first clock generator that generates a first clock signal having a first period from an input clock signal, a second clock generator that generates a second clock signal having a second period from the input clock signal, and a timing generator that receives the first clock signal, the second clock signal, an activation signal from a command decoder and a selection signal for selecting the delay time from a timing register to produce a timing signal delayed as from activation of the activation signal by a delay equal to a sum of a time equal to a preset number m prescribed by the selection signal times the first period and a time equal to another preset number n prescribed by the selection signal times the second period. The timing register holds the values of m and n. These values are set in the timing register in an initialization sequence at the time of a mode register set command. In the operating states, the timing signals are output from the timing generator at a desired timing based on the information stored in the timing register (FIG. 6).

    Abstract translation: 公开了一种半导体器件，包括第一时钟发生器，其从输入时钟信号产生具有第一周期的第一时钟信号;第二时钟发生器，其从输入时钟信号产生具有第二周期的第二时钟信号;以及定时发生器 其接收第一时钟信号，第二时钟信号，来自命令解码器的激活信号和用于从定时寄存器选择延迟时间的选择信号，以产生从激活信号的激活延迟等于 等于由选择信号规定的预定数量m的时间等于第一周期的时间和等于由选择信号规定的另一个预设数量n的时间乘以第二周期的时间之和。 定时寄存器保存m和n的值。 这些值在模式寄存器设置命令时以初始化顺序设置在定时寄存器中。 在操作状态下，基于定时寄存器（图6）中存储的信息，定时信号以定时发生器输出。

    Duty detection circuit, DLL circuit using the same, semiconductor memory circuit, and data processing system
    6.
    发明授权
    Duty detection circuit, DLL circuit using the same, semiconductor memory circuit, and data processing system 有权
    占空比检测电路，使用相同的DLL电路，半导体存储器电路和数据处理系统

    公开(公告)号：US07719921B2

    公开(公告)日：2010-05-18

    申请号：US12170730

    申请日：2008-07-10

    Applicant: Koji Kuroki ,  Yasuhiro Takai

    Inventor： Koji Kuroki ,  Yasuhiro Takai

    IPC: G11C11/00

    CPC classification number: G11C11/4076 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/087

    Abstract: A duty detection circuit includes discharge transistors, charge transistors, detection lines, and a comparator circuit that detects a potential difference of these detection lines, and also includes a gate circuit that controls the discharge transistors and the charge transistors in response to the internal clock signal of an even cycle. As a result, the detection lines are charged and discharged in response to the internal clock signal of the even cycle. Consequently, the duty detection circuit can be applied to a multi-phase DLL circuit, and a potential difference appearing in the detection line can be sufficiently secured.

    Abstract translation: 占空比检测电路包括放电晶体管，充电晶体管，检测线和检测这些检测线的电位差的比较器电路，还包括根据内部时钟信号控制放电晶体管和充电晶体管的门电路 的偶数周期。 结果，响应于偶数周期的内部时钟信号，检测线被充电和放电。 因此，占空比检测电路可以应用于多相DLL电路，并且可以充分确保出现在检测线中的电位差。

    ROLLER DRIVE CONTROL METHOD OF FIXING APPARATUS AND FIXING APPARATUS
    8.
    发明申请
    ROLLER DRIVE CONTROL METHOD OF FIXING APPARATUS AND FIXING APPARATUS 有权
    固定装置和固定装置的滚子驱动控制方法

    公开(公告)号：US20080253790A1

    公开(公告)日：2008-10-16

    申请号：US11839621

    申请日：2007-08-16

    Applicant: Yoshinobu TATEISHI ,  Yasuhiro Takai

    Inventor： Yoshinobu TATEISHI ,  Yasuhiro Takai

    IPC: G03G15/20

    CPC classification number: G03G15/2025 ,  G03G15/2028

    Abstract: In one embodiment, a predetermined period different from a fixing process period in which fixing of toner to recording paper is carried out is set as a toner removal period, and during the toner removal period a hot roller and a pressure roller are intermittently rotated, and separation claws in contact with the rollers are caused to vibrate by the intermittent rotation of the rollers such that toner adhered to the separation claws is caused to drop due to this and is removed. Also, faces of the separation claws that oppose the surfaces of the hot roller and the pressure roller are set in a convex shape.

    Abstract translation: 在一个实施例中，与执行调色剂到记录纸的定影的定影处理周期不同的预定时间段被设置为调色剂去除期间，并且在调色剂移除期间，热辊和加压辊间歇地旋转， 与辊接触的分离爪通过辊的间歇旋转而振动，使得附着在分离爪上的调色剂由此而下降，并被除去。 此外，与热辊和加压辊的表面相对的分离爪的面被设定为凸形。

    VOLTAGE CONTROLLED OSCILLATOR
    9.
    发明申请
    VOLTAGE CONTROLLED OSCILLATOR 有权
    电压控制振荡器

    公开(公告)号：US20080197932A1

    公开(公告)日：2008-08-21

    申请号：US12031809

    申请日：2008-02-15

    Applicant: Yasuhiro TAKAI

    Inventor： Yasuhiro TAKAI

    IPC: H03K3/03

    CPC classification number: H03K3/0322 ,  H03K5/133 ,  H03L7/0995

    Abstract: A voltage controlled oscillator that is a differential ring oscillator type voltage controlled oscillator that, by connecting in cascade differential delay elements to which differential clock signals of a mutually reverse phase are input and controlling the current that flows to the differential delay elements by a bias voltage, controls a delay amount of this differential clock signal, having a phase detection portion that outputs a detection signal by comparing an output voltage of the differential output of any differential delay element and a reference voltage that is set to a voltage that detects an abnormal operation, and a cross-coupled circuit that is provided at each of the differential delay elements and, when the detection signal is input, amplifies the potential difference between the pair of differential output terminals.

    Abstract translation: 一种压控振荡器，其是差分环形振荡器型压控振荡器，其通过连接到级联差分延迟元件中，相位反相的差分时钟信号被输入到差分延迟元件中，并且通过偏置电压来控制流向差分延迟元件的电流 控制该差分时钟信号的延迟量，具有相位检测部分，该相位检测部分通过比较任何差分延迟元件的差分输出的输出电压和设置为检测异常运算的电压的参考电压来输出检测信号 以及设置在每个差分延迟元件处的交叉耦合电路，并且当输入检测信号时，放大该对差分输出端子之间的电位差。

    IMAGE FORMING APPARATUS
    10.
    发明申请
    IMAGE FORMING APPARATUS 有权
    图像形成装置

    公开(公告)号：US20080013971A1

    公开(公告)日：2008-01-17

    申请号：US11774654

    申请日：2007-07-09

    Applicant: Masahiko Fujita ,  Tadasu Taniguchi ,  Norichika Katsura ,  Yasunobo Ohkawa ,  Yasuhiro Takai

    Inventor： Masahiko Fujita ,  Tadasu Taniguchi ,  Norichika Katsura ,  Yasunobo Ohkawa ,  Yasuhiro Takai

    IPC: G03G15/00 ,  G03G15/20 ,  G03G15/23

    CPC classification number: G03G15/235

    Abstract: In one embodiment of the invention, in an image forming apparatus that reverses the front and back of recording paper by performing switchback transport of the recording paper to perform duplex printing of the recording paper, the image forming apparatus is provided with a control means that, when performing duplex printing of the recording paper, forms a void area at a leading end and a trailing end of the recording paper, the void area preventing curling of the recording paper around a roller.

    Abstract translation: 在本发明的一个实施例中，在通过执行记录纸的转回传送以进行记录纸的双面打印来反转记录纸的前后的图像形成装置中，图像形成装置设置有控制装置， 当执行记录纸的双面打印时，在记录纸的前端和后端形成空隙区域，空隙区域防止记录纸卷绕在辊周围。

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