公开(公告)号：US5675331A

公开(公告)日：1997-10-07

申请号：US572100

申请日：1995-12-14

申请人： Hiromi Watanabe ,  Hiroki Mizosoe ,  Yukitoshi Tsuboi ,  Takayuki Miyo ,  Shuji Shinohara ,  Masuo Oku

发明人： Hiromi Watanabe ,  Hiroki Mizosoe ,  Yukitoshi Tsuboi ,  Takayuki Miyo ,  Shuji Shinohara ,  Masuo Oku

IPC分类号： H03M7/30 ,  H03M7/40 ,  H03M7/42

CPC分类号： H03M7/425 ,  H04N19/13 ,  H04N19/60 ,  H04N19/91

摘要： A decoding device is provided including a code FIFO memory unit for sequentially storing a bit stream, a barrel shifter for shifting and then outputting codes properly, an accumulator for computing the shift amount of the barrel shifter and issuing a request to read data to the code FIFO memory unit, a DCT coefficient decoder for decoding DCT coefficients, a variable-length code decoder for decoding variable-length codes other than DCT coefficients, a fixed-length code decoder for decoding fixed-length codes, a register unit for storing decoded data, a decoding controller for controlling the decoders in accordance with the decoded data stored in the register unit and decoded data output by the decoders and a memory controller for controlling operations to store DCT coefficients in a memory unit A. The DCT coefficient decoder, the variable-length code decoder and the fixed-length code decoder are connected in parallel to the output of the barrel shifter and the memory controller is controlled by the decoding controller. By virtue of this structure, the decoding device is capable decoding a bit stream comprising variable-length codes mixed with fixed-length codes. The decoding device is also capable of changing processing of a next code in accordance with decoded codes. Further, these operations can be implemented by means of a simple and reasonable configuration. On top of that, the process of decoding codes at a required high speed is carried out by an independent circuit, allowing the processing power of the decoding circuit to be enhanced.

摘要翻译： 提供一种解码装置，包括用于顺序存储位流的代码FIFO存储器单元，用于移位并随后正确输出代码的桶形移位器，用于计算桶形移位器的移位量并发出向代码读取数据的请求的累加器 FIFO存储单元，用于解码DCT系数的DCT系数解码器，用于解码除DCT系数之外的可变长度码的可变长度码解码器，用于解码固定长度码的固定长度码解码器，用于存储解码数据的寄存器单元 ，解码控制器，用于根据存储在寄存器单元中的解码数据和由解码器输出的解码数据来控制解码器;以及存储器控制器，用于控制将DCT系数存储在存储单元A中的操作。DCT系数解码器，变量 长码解码器和固定长度码解码器并联连接到桶形移位器的输出，并且存储器控制器是连续的 由解码控制器滚动。 通过这种结构，解码装置能够解码包含与固定长度码混合的可变长度码的比特流。 解码装置还能够根据解码的代码改变下一个代码的处理。 此外，这些操作可以通过简单合理的配置来实现。 此外，通过独立电路进行以所需高速解码的处理，能够提高解码电路的处理能力。