公开(公告)号：US20080086617A1

公开(公告)日：2008-04-10

申请号：US11865669

申请日：2007-10-01

申请人： Hironori KASAHARA ,  Keiji Kimura ,  Takashi Todaka ,  Tatsuya Kamei ,  Toshihiro Hattori

发明人： Hironori KASAHARA ,  Keiji Kimura ,  Takashi Todaka ,  Tatsuya Kamei ,  Toshihiro Hattori

IPC分类号： G06F13/00

CPC分类号： G06F15/167

摘要： To reduce overhead of data transfer between processor cores and improve a processing capability of a processor, there is provided a processor including: a CPU for performing computing processing; an internal memory for storing data; and a data transfer unit for performing data transfer between the internal memory and a shared memory, in which: the data transfer unit includes: a command chain module for executing a command sequence formed of a plurality of commands including a data transfer instruction; and a monitor module for reading data set in advance in the internal memory and repeatedly monitoring the data until a comparative value and a value of the data become equal to each other, when one of the plurality of commands of the command sequence thus read is a predetermined command; and the command chain module executes a next command in the command sequence after the monitor module has finished monitoring.

摘要翻译： 为了减少处理器核心之间的数据传输的开销并提高处理器的处理能力，提供了一种处理器，包括：用于执行计算处理的CPU; 用于存储数据的内部存储器; 以及数据传送单元，用于在内部存储器和共享存储器之间执行数据传送，其中：数据传送单元包括：命令链模块，用于执行由包括数据传送指令的多个命令形成的命令序列; 以及监视器模块，用于读取预先在内部存储器中设置的数据并重复监视数据，直到数据的比较值和值变得彼此相等时，当这样读取的命令序列的多个命令之一是 预定命令 命令链模块在监控模块完成监控后，在命令序列中执行下一个命令。

公开(公告)号：US20090193228A1

公开(公告)日：2009-07-30

申请号：US12358233

申请日：2009-01-22

申请人： Hironori KASAHARA ,  Keiji KIMURA ,  Masayuki ITO ,  Tatsuya KAMEI ,  Toshihiro HATTORI

发明人： Hironori KASAHARA ,  Keiji KIMURA ,  Masayuki ITO ,  Tatsuya KAMEI ,  Toshihiro HATTORI

IPC分类号： G06F15/76 ,  G06F9/06

CPC分类号： G06F15/16

摘要： Each of processors has a barrier write register and a barrier read register. Each barrier write register is wired to each barrier read register by a dedicated wiring block. For example, a 1-bit barrier write register of a processor is connected, via the wiring block, to a first bit of each 8-bit barrier read register contained in the processors, and a 1-bit barrier write register of another processor is connected, via a wiring block, to a second bit of each 8-bit barrier read register contained in the processors. For example, a processor writes information to its own barrier write register, thereby notifying synchronization stand-by to the other processors and reads its own barrier read register, thereby recognizing whether the other processors are in synchronization stand-by or not. Therefore, a special dedicated instruction is not required along barrier synchronization processing, and the processing can be made at a high speed.

摘要翻译： 每个处理器都有一个屏障写入寄存器和一个屏障读取寄存器。 每个屏障写入寄存器通过专用接线块连接到每个屏障读取寄存器。 例如，处理器的1位屏障写入寄存器经由布线块连接到处理器中包含的每个8位屏障读取寄存器的第一位，而另一个处理器的1位屏障写入寄存器是 通过接线块连接到处理器中包含的每个8位屏障读取寄存器的第二位。 例如，处理器将信息写入其自己的屏障写入寄存器，从而通知其他处理器的同步待机并读取其自己的障碍读取寄存器，从而识别其他处理器是否处于同步待机状态。 因此，沿着屏障同步处理不需要特殊的专用指令，并且可以高速进行处理。