摘要:
To reduce overhead of data transfer between processor cores and improve a processing capability of a processor, there is provided a processor including: a CPU for performing computing processing; an internal memory for storing data; and a data transfer unit for performing data transfer between the internal memory and a shared memory, in which: the data transfer unit includes: a command chain module for executing a command sequence formed of a plurality of commands including a data transfer instruction; and a monitor module for reading data set in advance in the internal memory and repeatedly monitoring the data until a comparative value and a value of the data become equal to each other, when one of the plurality of commands of the command sequence thus read is a predetermined command; and the command chain module executes a next command in the command sequence after the monitor module has finished monitoring.
摘要:
To reduce overhead of data transfer between processor cores and improve a processing capability of a processor, there is provided a processor including: a CPU for performing computing processing; an internal memory for storing data; and a data transfer unit for performing data transfer between the internal memory and a shared memory, in which: the data transfer unit includes: a command chain module for executing a command sequence formed of a plurality of commands including a data transfer instruction; and a monitor module for reading data set in advance in the internal memory and repeatedly monitoring the data until a comparative value and a value of the data become equal to each other, when one of the plurality of commands of the command sequence thus read is a predetermined command; and the command chain module executes a next command in the command sequence after the monitor module has finished monitoring.
摘要:
A system and method are disclosed to prevent a reduction in the number of I/O devices which can be connected when building a PCIe topology by connecting I/O devices to a computer via a PCIe switch. A switch with which a computer and I/O devices are connected includes: a first PCI-PCI bridge which is positioned on the computer side; a second PCI-PCI bridge which is positioned on the I/O device side; trapper units which trap packet data which is inputted into the switch; a packet routing unit which transfers packet data to the I/O devices; and a management processor which is connected to the trapper units and provides the computer a virtual PCI-PCI bridge and a virtual link by execution of a program. The trapper units adjudicate the destination of the packet data which is transferred from the computer.
摘要:
A system and method are disclosed to prevent a reduction in the number of I/O devices which can be connected when building a PCIe topology by connecting I/O devices to a computer via a PCIe switch. A switch with which a computer and I/O devices are connected includes: a first PCI-PCI bridge which is positioned on the computer side; a second PCI-PCI bridge which is positioned on the I/O device side; trapper units which trap packet data which is inputted into the switch; a packet routing unit which transfers packet data to the I/O devices; and a management processor which is connected to the trapper units and provides the computer a virtual PCI-PCI bridge and a virtual link by execution of a program. The trapper units adjudicate the destination of the packet data which is transferred from the computer.
摘要:
The present invention eliminates the shortage of bus numbers in routing control using PCIe switches. A system port address (SPA) is associated with a destination bus number and is assigned to a port (external port) connected to a server and a device. When packets sent from the server or the device are received at the external port, the system port address (SPA) corresponding to the destination bus number having the packets is determined, and the SPA is added to the packets as a label. This SPA is used to route the packets sent between ports (internal ports) that connect switches. When the packets arrive at the external port to which the target server or device is connected, the destination bus number having packets is used to send the packets to the server or device connected to the external port.
摘要:
The present invention eliminates the shortage of bus numbers in routing control using PCIe switches. A system port address (SPA) is associated with a destination bus number and is assigned to a port (external port) connected to a server and a device. When packets sent from the server or the device are received at the external port, the system port address (SPA) corresponding to the destination bus number having the packets is determined, and the SPA is added to the packets as a label. This SPA is used to route the packets sent between ports (internal ports) that connect switches. When the packets arrive at the external port to which the target server or device is connected, the destination bus number having packets is used to send the packets to the server or device connected to the external port.
摘要:
A processor includes a CPU capable of performing predetermined arithmetic processing, a memory accessible by the CPU, and a data transfer unit capable of controlling data transfer with the memory by substituting for the CPU. The data transfer unit is provided with a command chain unit for continuously performing data transfer by execution of a preset command chain, and a retry controller for executing a retry processing in case a transfer error occurs during data transfer by the command chain unit. Then, the data transfer unit reports a command relating to the transfer error to the CPU after completion of the execution of the command chain, thereby lessening the number of interruptions for error processing, and attaining enhancement in performance of a system.