公开(公告)号：US20120066563A1

公开(公告)日：2012-03-15

申请号：US13043918

申请日：2011-03-09

申请人： Haruka OBATA ,  Hironori Uchikawa

发明人： Haruka OBATA ,  Hironori Uchikawa

IPC分类号： H03M13/05

CPC分类号： H03M13/658 ,  H03M13/1111 ,  H03M13/112 ,  H03M13/1128 ,  H03M13/6583

摘要： According to an embodiment, an error correction decoder carries out iterative decoding for data coded using an irregular LDPC code. The decoder includes a likelihood control unit. The likelihood control unit is configured to carry out weighting using first extrinsic value weights when a first condition including a condition that a code word cannot be obtained even when number of times the iterative decoding has been carried out is greater than a first iterative times, in order to increase absolute value of a extrinsic value from a check node not satisfying a parity check to a variable node, wherein the first extrinsic value weights are equal to each other or become larger in descending order of column weights of the variable nodes, and a maximum of the first extrinsic value weights is not equal to a minimum of the first extrinsic value weights.

摘要翻译： 根据实施例，纠错解码器对使用不规则LDPC码编码的数据进行迭代解码。 解码器包括可能性控制单元。 似然度控制单元被配置为，在包括即使执行迭代解码的次数大于第一迭代次数的情况下也不能获得代码字的条件的第一条件下，使用第一非本征值权重进行加权， 为了从不满足奇偶校验的校验节点向变量节点增加非本征值的绝对值，其中，第一非本征值权重彼此相等，或者以可变节点的列权重的降序变大，并且 第一非本征值权重的最大值不等于第一外在值权重的最小值。

公开(公告)号：US08751895B2

公开(公告)日：2014-06-10

申请号：US13569492

申请日：2012-08-08

申请人： Haruka Obata ,  Tatsuyuki Ishikawa ,  Hironori Uchikawa ,  Kenji Sakurada

发明人： Haruka Obata ,  Tatsuyuki Ishikawa ,  Hironori Uchikawa ,  Kenji Sakurada

IPC分类号： H03M13/00

CPC分类号： H03M13/112 ,  H03M13/1128 ,  H03M13/6583

摘要： A semiconductor memory device includes a semiconductor memory unit which stores LDPC encoded data, and a decoding unit which decodes the encoded data, wherein the decoding unit performs serial decoding using the posterior likelihood ratio as it is for a column element likelihood ratio when the absolute value of the posterior likelihood ratio is not smaller than a threshold and using the column element likelihood ratio as it is for the posterior likelihood ratio when the absolute value of the column element likelihood ratio is not smaller than the threshold, and if the decoding does not succeed even after a predetermined first cycle count of iterative processing is performed or if the number of syndrome errors becomes smaller than a predetermined first syndrome error count, the decoding unit shrinks the absolute values of at least some of posterior likelihood ratios and resets all prior likelihood ratios to “0.”

摘要翻译： 半导体存储器件包括存储LDPC编码数据的半导体存储器单元和对编码数据进行解码的解码单元，其中，当绝对值为0时，解码单元使用后验似然比原理进行串行译码， 的后验似率比不小于阈值，并且当列元素似然比的绝对值不小于阈值时，使用列元素似然比作为后验似然比，并且如果解码不成功 即使在执行了预定的第一循环计数的迭代处理之后，或者如果校正子错误的数量变得小于预定的第一校正子错误计数，则解码单元收缩至少一些后验似然比的绝对值并且重置所有先验似然比 到“0”

公开(公告)号：US08966351B2

公开(公告)日：2015-02-24

申请号：US13706663

申请日：2012-12-06

申请人： Hironori Uchikawa ,  Haruka Obata

发明人： Hironori Uchikawa ,  Haruka Obata

IPC分类号： H03M13/00 ,  H03M13/13 ,  H03M13/11

CPC分类号： H03M13/13 ,  H03M13/116 ,  H03M13/118 ,  H03M13/611

摘要： According to one embodiment, an encoding apparatus includes an input unit and a generation unit. The input unit inputs a data symbol sequence containing q(N−J) symbols (q, J, and N are integers, N>J). The generation unit generates a codeword containing qN symbols by adding a parity symbol sequence containing qJ symbols to the data symbol sequence. The codeword satisfies parity check equations of a parity check matrix of qJ rows×qN columns. A first submatrix of qJ rows×qJ columns that corresponds to the parity symbol sequence in the parity check matrix includes a second submatrix. The second submatrix includes a first identity matrix of qL rows×qL columns (L is an integer, J>L) and a first non-zero matrix of q(J−L) rows×qL columns.

摘要翻译： 根据一个实施例，编码装置包括输入单元和生成单元。 输入单元输入包含q（N-J）个符号（q，J和N是整数N> J）的数据符号序列。 生成单元通过将包含qJ个符号的奇偶校验符号序列添加到数据符号序列来生成包含qN符号的码字。 码字满足qJ行×qN列的奇偶校验矩阵的奇偶校验方程。 对应于奇偶校验矩阵中的奇偶校验符号序列的qJ行×qJ列的第一子矩阵包括第二子矩阵。 第二子矩阵包括qL行×qL列（L是整数J> L）和q（J-L）行×qL列的第一非零矩阵的第一单位矩阵。

公开(公告)号：US08645802B2

公开(公告)日：2014-02-04

申请号：US13225759

申请日：2011-09-06

申请人： Haruka Obata ,  Hironori Uchikawa

发明人： Haruka Obata ,  Hironori Uchikawa

IPC分类号： H03M13/00

CPC分类号： H03M13/1142 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/451 ,  H03M13/458

摘要： According to embodiments, an error correction decoder carrying out iterative decoding for coded data based on LDPC code. The decoder comprises a generation unit and an inversion, control unit. The generation unit is configured to generate an inversion node list listing variable nodes connected to check nodes not satisfying a parity check when a code word cannot be obtained after carrying out the iterative decoding a first number of iterations. The inversion control unit is configured to choose a variable node which is a target for inversion from among the variable nodes listed in the inversion node list, and to carry out inversion processing which includes updating an input likelihood of the variable node which is the target for inversion temporarily by inverting a sign of an a posteriori likelihood of the variable node which is the target for inversion.

摘要翻译： 根据实施例，纠错解码器基于LDPC码对编码数据进行迭代解码。 解码器包括生成单元和反转控制单元。 生成单元被配置为生成反转节点列表，其列出了在执行迭代解码第一迭代次数之后不能获得码字时，连接到校验节点不满足奇偶校验的变量节点。 反转控制单元被配置为从反转节点列表中列出的可变节点中选择作为反转的目标的变量节点，并且执行包括更新作为目标的可变节点的输入似然性的反演处理 通过反转作为反转目标的可变节点的后验似然度的符号来临时反转。

公开(公告)号：US20120226954A1

公开(公告)日：2012-09-06

申请号：US13225759

申请日：2011-09-06

申请人： Haruka Obata ,  Hironori Uchikawa

发明人： Haruka Obata ,  Hironori Uchikawa

IPC分类号： H03M13/11 ,  G06F11/10

CPC分类号： H03M13/1142 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/451 ,  H03M13/458

摘要： According to embodiments, an error correction decoder carrying out iterative decoding for coded data based on LDPC code. The decoder comprises a generation unit and an inversion, control unit. The generation unit is configured to generate an inversion node list listing variable nodes connected to check nodes not satisfying a parity check when a code word cannot be obtained after carrying out the iterative decoding a first number of iterations. The inversion control unit is configured to choose a variable node which is a target for inversion from among the variable nodes listed in the inversion node list, and to carry out inversion processing which includes updating an input likelihood of the variable node which is the target for inversion temporarily by inverting a sign of an a posteriori likelihood of the variable node which is the target for inversion.

摘要翻译： 根据实施例，纠错解码器基于LDPC码对编码数据进行迭代解码。 解码器包括生成单元和反转控制单元。 生成单元被配置为生成反转节点列表，其列出了在执行迭代解码第一迭代次数之后不能获得码字时，连接到校验节点不满足奇偶校验的变量节点。 反转控制单元被配置为从反转节点列表中列出的可变节点中选择作为反转的目标的变量节点，并且执行包括更新作为目标的可变节点的输入似然性的反演处理 通过反转作为反转目标的可变节点的后验似然度的符号来临时反转。

公开(公告)号：US20120240008A1

公开(公告)日：2012-09-20

申请号：US13363667

申请日：2012-02-01

申请人： Haruka OBATA ,  Hironori Uchikawa

发明人： Haruka OBATA ,  Hironori Uchikawa

IPC分类号： G06F11/08

CPC分类号： H03M13/118 ,  H03M13/611

摘要： According to an embodiment, an encoder has a storage and a generator. The storage stores information indicative of a generator matrix corresponding to a partial parity check matrix in a rank-deficient parity check matrix including a lower triangular matrix and one or more cyclic matrices or zero matrices, the partial parity check matrix including rows different from rows of the lower triangular matrix. The generator carries out semi-systematic coding using the generator matrix to generate a portion of code word. The generator matrix has a cyclic matrix portion with one or more cyclic matrices and a non-cyclic matrix portion with rows number of which is equal to a degree of rank deficiency in the partial parity check matrix.

摘要翻译： 根据实施例，编码器具有存储器和发生器。 存储器存储指示与包括下三角矩阵和一个或多个循环矩阵或零矩阵的秩缺陷奇偶校验矩阵中的部分奇偶校验矩阵相对应的生成矩阵的信息，该部分奇偶校验矩阵包括与 下三角矩阵。 发生器使用发生器矩阵执行半系统编码以产生代码字的一部分。 发生器矩阵具有循环矩阵部分，其具有一个或多个循环矩阵和非循环矩阵部分，其行数等于部分奇偶校验矩阵中的秩缺陷度。

公开(公告)号：US08572465B2

公开(公告)日：2013-10-29

申请号：US12848476

申请日：2010-08-02

申请人： Hironori Uchikawa ,  Yoshihisa Kondo

发明人： Hironori Uchikawa ,  Yoshihisa Kondo

IPC分类号： G06F11/00

CPC分类号： G06F11/10 ,  H03M13/05 ,  Y02D10/13

摘要： A nonvolatile semiconductor memory system includes a semiconductor memory, at least one first error correction unit and at least one second error correction unit. The semiconductor memory stores a data frame encoded with LDPC codes. The at least one first error correction unit performs a first error correction for the data frame according to a first iterative decoding algorithm. The at least one second error correction unit performs a second error correction for the data frame which is failed to correct error by the at least one first error correction unit. The at least one second error correction unit performs the second error correction according to a second iterative decoding algorithm which uses a message having a larger number of quantization bits than that of the first iterative decoding algorithm.

摘要翻译： 非易失性半导体存储器系统包括半导体存储器，至少一个第一纠错单元和至少一个第二纠错单元。 半导体存储器存储用LDPC码编码的数据帧。 所述至少一个第一纠错单元根据第一迭代解码算法对所述数据帧执行第一纠错。 所述至少一个第二纠错单元对由所述至少一个第一误差校正单元校正错误的数据帧执行第二纠错。 所述至少一个第二纠错单元根据使用具有比第一迭代解码算法的量化位数更多的量化消息的消息的第二迭代解码算法执行第二纠错。

公开(公告)号：US08332726B2

公开(公告)日：2012-12-11

申请号：US13310003

申请日：2011-12-02

申请人： Hironori Uchikawa ,  Tatsuyuki Ishikawa ,  Mitsuaki Honma

发明人： Hironori Uchikawa ,  Tatsuyuki Ishikawa ,  Mitsuaki Honma

IPC分类号： G11C29/00

CPC分类号： G06F11/1068 ,  G11C2029/0411

摘要： A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information in accordance with variations in threshold voltage. A likelihood calculator has a plurality of likelihood calculation algorithms for deriving a likelihood value about a stored data bit from a threshold value read out of the memory cell. An error correction unit executes error correction through iterative processing using the likelihood value obtained at the likelihood calculator. A likelihood calculator controller changes among the likelihood calculation algorithms in the likelihood calculator based on a certain value of the number of iterations in the iterative processing obtained from the error correction unit.

摘要翻译： 非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括能够根据阈值电压的变化存储信息的多个存储单元。 似然度计算器具有多个似然计算算法，用于从从存储单元读出的阈值中导出关于存储的数据位的似然值。 错误校正单元通过使用在似然度计算器获得的似然值的迭代处理执行纠错。 似然度计算器控制器根据从误差校正单元获得的迭代处理中的迭代次数的一定值，在似然度计算器中的似然计算算法中进行变化。

公开(公告)号：US08149623B2

公开(公告)日：2012-04-03

申请号：US12715772

申请日：2010-03-02

申请人： Hironori Uchikawa ,  Kenji Sakurada

发明人： Hironori Uchikawa ,  Kenji Sakurada

IPC分类号： G11C16/04

CPC分类号： G11C11/5642 ,  G11C16/34

摘要： A controller includes a generation unit configured to aggregate comparison results between second threshold voltage levels held in the memory cells and predetermined third threshold voltage levels, and generate a histogram of the second threshold voltage levels, an estimation unit configured to estimate statistical parameter of a distribution of the second threshold voltage levels with respect to a first threshold voltage level according to writing data, based on the histogram, and a determination unit configured to determine a fifth threshold voltage level defining a boundary of a fourth threshold voltage level indicating a read result of the memory cells from the third threshold voltage levels based on the statistical parameter in such a manner that mutual information amount between the first threshold voltage level and the fourth threshold voltage level becomes maximum.

摘要翻译： 控制器包括：生成单元，被配置为将存储单元中保持的第二阈值电压电平与预定的第三阈值电压电平之间的比较结果进行聚合，并生成第二阈值电压电平的直方图;估计单元，被配置为估计分布的统计参数 基于所述直方图，根据写入数据相对于第一阈值电压电平的第二阈值电压电平，以及确定单元，被配置为确定第五阈值电压电平，所述第五阈值电压电平定义指示读取结果的第四阈值电压电平的边界 基于所述统计参数从所述第三阈值电压电平的所述存储器单元，使得所述第一阈值电压电平和所述第四阈值电压电平之间的相互信息量变为最大。

公开(公告)号：US20110219284A1

公开(公告)日：2011-09-08

申请号：US12848476

申请日：2010-08-02

申请人： Hironori Uchikawa ,  Yoshihisa Kondo

发明人： Hironori Uchikawa ,  Yoshihisa Kondo

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G06F11/10 ,  H03M13/05 ,  Y02D10/13

摘要： A nonvolatile semiconductor memory system includes a semiconductor memory, at least one first error correction unit and at least one second error correction unit. The semiconductor memory stores a data frame encoded with LDPC codes. The at least one first error correction unit performs a first error correction for the data frame according to a first iterative decoding algorithm. The at least one second error correction unit performs a second error correction for the data frame which is failed to correct error by the at least one first error correction unit. The at least one second error correction unit performs the second error correction according to a second iterative decoding algorithm which uses a message having a larger number of quantization bits than that of the first iterative decoding algorithm.

摘要翻译： 非易失性半导体存储器系统包括半导体存储器，至少一个第一纠错单元和至少一个第二纠错单元。 半导体存储器存储用LDPC码编码的数据帧。 所述至少一个第一纠错单元根据第一迭代解码算法对所述数据帧执行第一纠错。 所述至少一个第二纠错单元对由所述至少一个第一误差校正单元校正错误的数据帧执行第二纠错。 所述至少一个第二纠错单元根据使用具有比第一迭代解码算法的量化位数更多的量化消息的消息的第二迭代解码算法执行第二纠错。