公开(公告)号：US20130111292A1

公开(公告)日：2013-05-02

申请号：US13569492

申请日：2012-08-08

申请人： Haruka OBATA ,  Tatsuyuki ISHIKAWA ,  Hironori UCHIKAWA ,  Kenji SAKURADA

发明人： Haruka OBATA ,  Tatsuyuki ISHIKAWA ,  Hironori UCHIKAWA ,  Kenji SAKURADA

IPC分类号： H03M13/05

CPC分类号： H03M13/112 ,  H03M13/1128 ,  H03M13/6583

摘要： A semiconductor memory device includes a semiconductor memory unit which stores LDPC encoded data, and a decoding unit which decodes the encoded data, wherein the decoding unit performs serial decoding using the posterior likelihood ratio as it is for a column element likelihood ratio when the absolute value of the posterior likelihood ratio is not smaller than a threshold and using the column element likelihood ratio as it is for the posterior likelihood ratio when the absolute value of the column element likelihood ratio is not smaller than the threshold, and if the decoding does not succeed even after a predetermined first cycle count of iterative processing is performed or if the number of syndrome errors becomes smaller than a predetermined first syndrome error count, the decoding unit shrinks the absolute values of at least some of posterior likelihood ratios and resets all prior likelihood ratios to “0.”

摘要翻译： 半导体存储器件包括存储LDPC编码数据的半导体存储器单元和对编码数据进行解码的解码单元，其中，当绝对值为0时，解码单元使用后验似然比原理进行串行解码，作为列元素似然比 的后验似率比不小于阈值，并且当列元素似然比的绝对值不小于阈值时，使用列元素似然比作为后验似然比，并且如果解码不成功 即使在执行了预定的第一循环计数的迭代处理之后，或者如果校正子错误的数量变得小于预定的第一校正子错误计数，则解码单元收缩至少一些后验似然比的绝对值并且重置所有先验似然比 到“0”

公开(公告)号：US20120224420A1

公开(公告)日：2012-09-06

申请号：US13233530

申请日：2011-09-15

申请人： Kenji Sakurada ,  Hironori Uchikawa

发明人： Kenji Sakurada ,  Hironori Uchikawa

IPC分类号： G11C16/26

CPC分类号： G11C11/5642 ,  G11C8/08

摘要： A memory card decodes three bits of data stored in one memory cell and belonging to different pages, each being a unit of reading, by iterative calculation using probability based on eight threshold voltage distributions. The memory card includes a word line controlling section configured to select one required to read 1-bit data belonging to one of the pages to be read from among seven voltage sets which are composed of seven reference voltages for hard bit reading and a plurality of intermediate voltages for soft bit reading and perform control to apply the voltages of the selected voltage set as read voltages to the memory cell, a log likelihood ratio table storing section, and a decoder configured to decode read data using a log likelihood ratio.

摘要翻译： 存储卡通过使用基于八个阈值电压分布的概率的迭代计算来解码存储在一个存储器单元中的三位数据，并且属于不同页面，每一页都是读取单元。 存储卡包括字线控制部，被配置为从由七个用于硬比特读取的参考电压和多个中间值组成的七个电压组中选择要读取属于要读取的一个页面的1位数据所需的一个 用于软位读取的电压，并且执行控制以将所设置的所选电压的电压设置为读取电压到存储器单元，对数似然比表存储部分和被配置为使用对数似然比来解码读取数据的解码器。

公开(公告)号：US08250437B2

公开(公告)日：2012-08-21

申请号：US12796211

申请日：2010-06-08

申请人： Kenji Sakurada ,  Hironori Uchikawa

发明人： Kenji Sakurada ,  Hironori Uchikawa

IPC分类号： G11C29/00

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C29/00

摘要： A memory system in an embodiment having a host and a memory card, including: a plurality of semiconductor memory cells, each cell being configured to store N-bit coded data based on threshold voltage distributions; an LLR table storage section configured to store a first LLR table that consists of normal LLR data corresponding to predetermined threshold voltages and a second LLR table that consists of LLR data such that two LLRs at each location corresponding to each location in the first LLR table at which a sign is inverted between two adjacent LLRs are “0”; and a decoder configured to perform decoding processing through probability-based repeated calculations using an LLR.

摘要翻译： 具有主机和存储卡的实施例中的存储器系统包括：多个半导体存储器单元，每个单元被配置为基于阈值电压分布来存储N位编码数据; LLR表存储部分，被配置为存储由对应于预定阈值电压的正常LLR数据组成的第一LLR表和由LLR数据构成的第二LLR表，使得在与第一LLR表中的每个位置对应的每个位置处的两个LLR 两个相邻LLR之间的符号被反转的是“0”; 以及解码器，被配置为使用LLR执行基于概率的重复计算的解码处理。

公开(公告)号：US08751895B2

公开(公告)日：2014-06-10

申请号：US13569492

申请日：2012-08-08

申请人： Haruka Obata ,  Tatsuyuki Ishikawa ,  Hironori Uchikawa ,  Kenji Sakurada

发明人： Haruka Obata ,  Tatsuyuki Ishikawa ,  Hironori Uchikawa ,  Kenji Sakurada

IPC分类号： H03M13/00

CPC分类号： H03M13/112 ,  H03M13/1128 ,  H03M13/6583

摘要： A semiconductor memory device includes a semiconductor memory unit which stores LDPC encoded data, and a decoding unit which decodes the encoded data, wherein the decoding unit performs serial decoding using the posterior likelihood ratio as it is for a column element likelihood ratio when the absolute value of the posterior likelihood ratio is not smaller than a threshold and using the column element likelihood ratio as it is for the posterior likelihood ratio when the absolute value of the column element likelihood ratio is not smaller than the threshold, and if the decoding does not succeed even after a predetermined first cycle count of iterative processing is performed or if the number of syndrome errors becomes smaller than a predetermined first syndrome error count, the decoding unit shrinks the absolute values of at least some of posterior likelihood ratios and resets all prior likelihood ratios to “0.”

摘要翻译： 半导体存储器件包括存储LDPC编码数据的半导体存储器单元和对编码数据进行解码的解码单元，其中，当绝对值为0时，解码单元使用后验似然比原理进行串行译码， 的后验似率比不小于阈值，并且当列元素似然比的绝对值不小于阈值时，使用列元素似然比作为后验似然比，并且如果解码不成功 即使在执行了预定的第一循环计数的迭代处理之后，或者如果校正子错误的数量变得小于预定的第一校正子错误计数，则解码单元收缩至少一些后验似然比的绝对值并且重置所有先验似然比 到“0”

公开(公告)号：US08149623B2

公开(公告)日：2012-04-03

申请号：US12715772

申请日：2010-03-02

申请人： Hironori Uchikawa ,  Kenji Sakurada

发明人： Hironori Uchikawa ,  Kenji Sakurada

IPC分类号： G11C16/04

CPC分类号： G11C11/5642 ,  G11C16/34

摘要： A controller includes a generation unit configured to aggregate comparison results between second threshold voltage levels held in the memory cells and predetermined third threshold voltage levels, and generate a histogram of the second threshold voltage levels, an estimation unit configured to estimate statistical parameter of a distribution of the second threshold voltage levels with respect to a first threshold voltage level according to writing data, based on the histogram, and a determination unit configured to determine a fifth threshold voltage level defining a boundary of a fourth threshold voltage level indicating a read result of the memory cells from the third threshold voltage levels based on the statistical parameter in such a manner that mutual information amount between the first threshold voltage level and the fourth threshold voltage level becomes maximum.

摘要翻译： 控制器包括：生成单元，被配置为将存储单元中保持的第二阈值电压电平与预定的第三阈值电压电平之间的比较结果进行聚合，并生成第二阈值电压电平的直方图;估计单元，被配置为估计分布的统计参数 基于所述直方图，根据写入数据相对于第一阈值电压电平的第二阈值电压电平，以及确定单元，被配置为确定第五阈值电压电平，所述第五阈值电压电平定义指示读取结果的第四阈值电压电平的边界 基于所述统计参数从所述第三阈值电压电平的所述存储器单元，使得所述第一阈值电压电平和所述第四阈值电压电平之间的相互信息量变为最大。

公开(公告)号：US20110038212A1

公开(公告)日：2011-02-17

申请号：US12715772

申请日：2010-03-02

申请人： Hironori Uchikawa ,  Kenji Sakurada

发明人： Hironori Uchikawa ,  Kenji Sakurada

IPC分类号： G11C16/04 ,  G11C7/00

CPC分类号： G11C11/5642 ,  G11C16/34

摘要： A controller includes a generation unit configured to aggregate comparison results between second threshold voltage levels held in the memory cells and predetermined third threshold voltage levels, and generate a histogram of the second threshold voltage levels, an estimation unit configured to estimate statistical parameter of a distribution of the second threshold voltage levels with respect to a first threshold voltage level according to writing data, based on the histogram, and a determination unit configured to determine a fifth threshold voltage level defining a boundary of a fourth threshold voltage level indicating a read result of the memory cells from the third threshold voltage levels based on the statistical parameter in such a manner that mutual information amount between the first threshold voltage level and the fourth threshold voltage level becomes maximum.

摘要翻译： 控制器包括：生成单元，被配置为将存储单元中保持的第二阈值电压电平与预定的第三阈值电压电平之间的比较结果进行聚合，并生成第二阈值电压电平的直方图;估计单元，被配置为估计分布的统计参数 基于所述直方图，根据写入数据相对于第一阈值电压电平的第二阈值电压电平，以及确定单元，被配置为确定第五阈值电压电平，所述第五阈值电压电平定义指示读取结果的第四阈值电压电平的边界 基于所述统计参数从所述第三阈值电压电平的所述存储器单元，使得所述第一阈值电压电平和所述第四阈值电压电平之间的相互信息量变为最大。

公开(公告)号：US20100223538A1

公开(公告)日：2010-09-02

申请号：US12622868

申请日：2009-11-20

申请人： Kenji SAKURADA

发明人： Kenji SAKURADA

IPC分类号： H03M13/00

CPC分类号： G06F11/1072 ,  H03M13/1102

摘要： A memory card including a word line control portion configured to perform control of applying intermediate voltages made up of a first intermediate voltage lower than a center voltage of four threshold voltage distributions and a second intermediate voltage higher than the center voltage to the memory cell, a logarithmic likelihood ratio table memory portion configured to store 9-level logarithmic likelihood ratios based on read voltages, and a decoder configured to perform decoding processing on the data read using the logarithmic likelihood ratio stored in the logarithmic likelihood ratio table memory portion.

摘要翻译： 一种存储卡，包括字线控制部分，被配置为执行将由低于四个阈值电压分布的中心电压的第一中间电压和高于中心电压的第二中间电压构成的中间电压施加到存储器单元的控制， 对数似然比表存储部，被配置为基于读取电压存储9级对数似然比;以及解码器，被配置为使用存储在对数似然比表存储器部分中的对数似然比对所读取的数据执行解码处理。

公开(公告)号：US08625347B2

公开(公告)日：2014-01-07

申请号：US13597444

申请日：2012-08-29

申请人： Kenji Sakurada

发明人： Kenji Sakurada

IPC分类号： G11C11/34

CPC分类号： G11C16/06 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/349

摘要： A memory card includes: a plurality of memory cells; a CPU core; and an ECC unit configured to perform soft decision decoding. If decoding based on an LLR acquired from a first LLR table fails, the memory card measures a threshold voltage distribution centered on a first HB read voltage with a highest voltage. If a first shift value as a difference between a least frequent voltage of the threshold voltage distribution and the first HB read voltage is “negative”, the memory card performs decoding based on an LLR acquired from the second LLR table. If the first shift value is “positive”, the memory card performs decoding based on an LLR acquired from a third LLR table.

摘要翻译： 存储卡包括：多个存储单元; 一个CPU核心; 以及被配置为执行软判决解码的ECC单元。 如果基于从第一LLR表获取的LLR的解码失败，则存储卡测量以具有最高电压的第一HB读取电压为中心的阈值电压分布。 如果作为阈值电压分布的最低频率电压与第一HB读取电压之间的差的第一偏移值为“负”，则存储卡基于从第二LLR表获取的LLR进行解码。 如果第一移位值为“正”，则存储卡基于从第三LLR表获取的LLR进行解码。

公开(公告)号：US20130077400A1

公开(公告)日：2013-03-28

申请号：US13597444

申请日：2012-08-29

申请人： Kenji SAKURADA

发明人： Kenji SAKURADA

IPC分类号： G11C16/10

CPC分类号： G11C16/06 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/349

摘要： A memory card includes: a plurality of memory cells; a CPU core; and an ECC unit configured to perform soft decision decoding. If decoding based on an LLR acquired from a first LLR table fails, the memory card measures a threshold voltage distribution centered on a first HB read voltage with a highest voltage. If a first shift value as a difference between a least frequent voltage of the threshold voltage distribution and the first HB read voltage is “negative”, the memory card performs decoding based on an LLR acquired from the second LLR table. If the first shift value is “positive”, the memory card performs decoding based on an LLR acquired from a third LLR table.

摘要翻译： 存储卡包括：多个存储单元; 一个CPU核心; 以及被配置为执行软判决解码的ECC单元。 如果基于从第一LLR表获取的LLR的解码失败，则存储卡测量以具有最高电压的第一HB读取电压为中心的阈值电压分布。 如果作为阈值电压分布的最低频率电压与第一HB读取电压之间的差的第一移位值为负，则存储卡基于从第二LLR表获取的LLR进行解码。 如果第一移位值为正，则存储卡基于从第三LLR表获取的LLR进行解码。

公开(公告)号：US08385117B2

公开(公告)日：2013-02-26

申请号：US13233530

申请日：2011-09-15

申请人： Kenji Sakurada ,  Hironori Uchikawa

发明人： Kenji Sakurada ,  Hironori Uchikawa

IPC分类号： G11C16/04

CPC分类号： G11C11/5642 ,  G11C8/08

摘要： A memory card decodes three bits of data stored in one memory cell and belonging to different pages, each being a unit of reading, by iterative calculation using probability based on eight threshold voltage distributions. The memory card includes a word line controlling section configured to select one required to read 1-bit data belonging to one of the pages to be read from among seven voltage sets which are composed of seven reference voltages for hard bit reading and a plurality of intermediate voltages for soft bit reading and perform control to apply the voltages of the selected voltage set as read voltages to the memory cell, a log likelihood ratio table storing section, and a decoder configured to decode read data using a log likelihood ratio.

摘要翻译： 存储卡通过使用基于八个阈值电压分布的概率的迭代计算来解码存储在一个存储器单元中的三位数据，并且属于不同页面，每一页都是读取单元。 存储卡包括字线控制部，被配置为从由七个用于硬比特读取的参考电压和多个中间值组成的七个电压组中选择要读取属于要读取的一个页面的1位数据所需的一个 用于软位读取的电压，并且执行控制以将所设置的所选电压的电压设置为读取电压到存储器单元，对数似然比表存储部分和被配置为使用对数似然比来解码读取数据的解码器。