Evaluation chip
    3.
    发明授权
    Evaluation chip 失效
    评估芯片

    公开(公告)号:US07159057B2

    公开(公告)日:2007-01-02

    申请号:US10989025

    申请日:2004-11-16

    IPC分类号: G06F9/46

    CPC分类号: G06F13/26

    摘要: An evaluation chip is disclosed whose interrupt priority order can be changed freely. A plurality of interrupt priority order determining circuits 20-1 to 2-4 perform a logical operation on a plurality of signals S11 to S14 used for interrupt priority order modifying control that are applied from outside and a plurality of interrupt signals S31-1 to S31-4, and output interrupt modifying signals S24-1 to S24-4. A plurality of interrupt modules 30-1 to 30-4 perform a logical AND operation on the plurality of signals S24-1 to S24-4 and a plurality of interrupt request signals S15-1 to S15-4 that are applied from outside, and output the signals S31-1 to S31-4. An address generating circuit 40 encodes the plurality of signals S31-1 to S31-4 and generates interrupt vector addresses 40. A microcomputer core 50 executes interrupt instructions that have been fetched from an external program memory 100, based on the addresses S40.

    摘要翻译: 公开了一种评估芯片,其中断优先顺序可以自由改变。 多个中断优先级顺序确定电路20-1至2-4对从外部施加的用于中断优先级顺序修改控制的多个信号S11至S14执行逻辑运算,并且多个中断信号S31- 1〜S 31〜4,输出中断修改信号S 24〜1〜S 24〜4。 多个中断模块30-1至30-4对多个信号S 24-1至S 24-4执行逻辑与运算,并施加多个中断请求信号S 15-1至S 15-4 并从外部输出信号S31-1到S31-4。 地址发生电路40对多个信号S31-1至S31-4进行编码,并产生中断向量地址40。 微计算机核心50基于地址S 40执行从外部程序存储器100取出的中断指令。

    Evaluation chip
    4.
    发明申请
    Evaluation chip 失效
    评估芯片

    公开(公告)号:US20050216636A1

    公开(公告)日:2005-09-29

    申请号:US10989025

    申请日:2004-11-16

    IPC分类号: G06F11/22 G06F11/36 G06F13/26

    CPC分类号: G06F13/26

    摘要: An evaluation chip is disclosed whose interrupt priority order can be changed freely. A plurality of interrupt priority order determining circuits 20-1 to 2-4 perform a logical operation on a plurality of signals S11 to S14 used for interrupt priority order modifying control that are applied from outside and a plurality of interrupt signals S31-1 to S31-4, and output interrupt modifying signals S24-1 to S24-4. A plurality of interrupt modules 30-1 to 30-4 perform a logical AND operation on the plurality of signals S24-1 to S24-4 and a plurality of interrupt request signals S15-1 to S15-4 that are applied from outside, and output the signals S31-1 to S31-4. An address generating circuit 40 encodes the plurality of signals S31-1 to S31-4 and generates interrupt vector addresses 40. A microcomputer core 50 executes interrupt instructions that have been fetched from an external program memory 100, based on the addresses S40.

    摘要翻译: 公开了一种评估芯片,其中断优先顺序可以自由改变。 多个中断优先级顺序确定电路20-1至2-4对从外部施加的用于中断优先级顺序修改控制的多个信号S11至S14执行逻辑运算,并且多个中断信号S31- 1〜S 31〜4,输出中断修改信号S 24〜1〜S 24〜4。 多个中断模块30-1至30-4对多个信号S 24-1至S 24-4执行逻辑与运算,并施加多个中断请求信号S 15-1至S 15-4 并从外部输出信号S31-1到S31-4。 地址发生电路40对多个信号S31-1至S31-4进行编码,并产生中断向量地址40。 微计算机核心50基于地址S 40执行从外部程序存储器100取出的中断指令。