公开(公告)号：US07868892B2

公开(公告)日：2011-01-11

申请号：US12237112

申请日：2008-09-24

申请人： Hirotaka Hara ,  Hiroyuki Hamasaki ,  Mitsuhiro Saeki ,  Kazuhiro Hirade ,  Makoto Takano

发明人： Hirotaka Hara ,  Hiroyuki Hamasaki ,  Mitsuhiro Saeki ,  Kazuhiro Hirade ,  Makoto Takano

IPC分类号： G06F13/14 ,  G06F13/36

CPC分类号： G06T11/203 ,  G06T1/20

摘要： An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.

摘要翻译： 本发明的一个目的是提高图形数据处理器中用于绘制和显示控制的控制信息，图形数据等的传送效率。 图形数据处理器包括：CPU; 耦合到CPU的第一个总线; 用于使用第一总线控制数据传输的DMAC; 用于向/从第一总线发送/接收数据的总线桥电路; 三维图形模块，用于经由第一总线从CPU接收命令并执行三维图形处理; 耦合到总线桥电路的第二总线和多个第一电路模块; 耦合到总线桥电路和第二电路模块的第三总线; 以及耦合到第一和第二总线和三维图形模块并且可连接到外部存储器的存储器接口电路，其中总线桥电路可以控制外部电路和第二总线之间的直接存储器访问传输。

公开(公告)号：US20050030311A1

公开(公告)日：2005-02-10

申请号：US10891047

申请日：2004-07-15

申请人： Hirotaka Hara ,  Hiroyuki Hamasaki ,  Mitsuhiro Saeki ,  Kazuhiro Hirade ,  Makoto Takano

发明人： Hirotaka Hara ,  Hiroyuki Hamasaki ,  Mitsuhiro Saeki ,  Kazuhiro Hirade ,  Makoto Takano

IPC分类号： G06F13/28 ,  G06F15/78 ,  G06T1/20 ,  G06T11/20 ,  G06T11/40 ,  G06T15/00 ,  G06T1/00 ,  G06F13/14

CPC分类号： G06T11/203 ,  G06T1/20

摘要： An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.

摘要翻译： 本发明的一个目的是提高图形数据处理器中绘图和显示控制的控制信息，图形数据等的传送效率。 图形数据处理器包括：CPU; 耦合到CPU的第一个总线; 用于使用第一总线控制数据传输的DMAC; 用于向/从第一总线发送/接收数据的总线桥电路; 三维图形模块，用于经由第一总线从CPU接收命令并执行三维图形处理; 耦合到总线桥电路的第二总线和多个第一电路模块; 耦合到总线桥电路和第二电路模块的第三总线; 以及耦合到第一和第二总线和三维图形模块并且可连接到外部存储器的存储器接口电路，其中总线桥电路可以控制外部电路和第二总线之间的直接存储器访问传输。

公开(公告)号：US07446775B2

公开(公告)日：2008-11-04

申请号：US10891047

申请日：2004-07-15

申请人： Hirotaka Hara ,  Hiroyuki Hamasaki ,  Mitsuhiro Saeki ,  Kazuhiro Hirade ,  Makoto Takano

发明人： Hirotaka Hara ,  Hiroyuki Hamasaki ,  Mitsuhiro Saeki ,  Kazuhiro Hirade ,  Makoto Takano

IPC分类号： G06F13/14 ,  G06F13/36

CPC分类号： G06T11/203 ,  G06T1/20

摘要： An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.

摘要翻译： 本发明的一个目的是提高图形数据处理器中绘图和显示控制的控制信息，图形数据等的传送效率。 图形数据处理器包括：CPU; 耦合到CPU的第一个总线; 用于使用第一总线控制数据传输的DMAC; 用于向/从第一总线发送/接收数据的总线桥电路; 三维图形模块，用于经由第一总线从CPU接收命令并执行三维图形处理; 耦合到总线桥电路的第二总线和多个第一电路模块; 耦合到总线桥电路和第二电路模块的第三总线; 以及耦合到第一和第二总线和三维图形模块并且可连接到外部存储器的存储器接口电路，其中总线桥电路可以控制外部电路和第二总线之间的直接存储器访问传输。

公开(公告)号：US20090015590A1

公开(公告)日：2009-01-15

申请号：US12237112

申请日：2008-09-24

申请人： HIROTAKA HARA ,  Hiroyuki Hamasaki ,  Mitsuhiro Saeki ,  Kazuhiro Hirade ,  Makoto Takano

发明人： HIROTAKA HARA ,  Hiroyuki Hamasaki ,  Mitsuhiro Saeki ,  Kazuhiro Hirade ,  Makoto Takano

IPC分类号： G06T15/00

CPC分类号： G06T11/203 ,  G06T1/20

摘要： An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.

摘要翻译： 本发明的一个目的是提高图形数据处理器中绘图和显示控制的控制信息，图形数据等的传送效率。 图形数据处理器包括：CPU; 耦合到CPU的第一个总线; 用于使用第一总线控制数据传输的DMAC; 用于向/从第一总线发送/接收数据的总线桥电路; 三维图形模块，用于经由第一总线从CPU接收命令并执行三维图形处理; 耦合到总线桥电路的第二总线和多个第一电路模块; 耦合到总线桥电路和第二电路模块的第三总线; 以及耦合到第一和第二总线和三维图形模块并且可连接到外部存储器的存储器接口电路，其中总线桥电路可以控制外部电路和第二总线之间的直接存储器访问传输。

公开(公告)号：US06697906B1

公开(公告)日：2004-02-24

申请号：US09561340

申请日：2000-04-28

申请人： Kazushige Ayukawa ,  Jun Sato ,  Takashi Miyamoto ,  Kenichiro Omura ,  Hiroyuki Hamasaki ,  Hiroshi Takeda ,  Makoto Takano ,  Isamu Mochizuki ,  Yasuhiko Hoshi ,  Kazuhiro Hirade ,  Ryuichi Murashima

发明人： Kazushige Ayukawa ,  Jun Sato ,  Takashi Miyamoto ,  Kenichiro Omura ,  Hiroyuki Hamasaki ,  Hiroshi Takeda ,  Makoto Takano ,  Isamu Mochizuki ,  Yasuhiko Hoshi ,  Kazuhiro Hirade ,  Ryuichi Murashima

IPC分类号： G06F100

CPC分类号： G06F13/4031

摘要： A semiconductor device is connected to a CPU, a memory and I/O devices to serve as a data transfer bridge for efficient data transfer between the memory and the I/O devices. A CPU interface and a plurality of I/O interfaces included in a bridge chip are connected through an internal bus to a memory interface included in the bridge chip. Each I/O interface has a read/write buffer and a DMAC. An arbiter included in the bridge chip determines a bus master for which data transfer is permitted in response to requests for data transfer from each of the CPU interface and the DMAC to the memory. Each of the I/O interfaces has a control function to skip part of areas in the memory when transferring data between the memory and the I/O interface.

摘要翻译： 半导体器件连接到CPU，存储器和I / O设备以用作用于在存储器和I / O设备之间进行有效数据传输的数据传输桥。 包括在桥芯片中的CPU接口和多个I / O接口通过内部总线连接到包括在桥芯片中的存储器接口。 每个I / O接口都有一个读/写缓冲区和一个DMAC。 包括在桥芯片中的仲裁器确定响应于从CPU接口和DMAC到存储器的数据传输的请求而允许数据传输的总线主机。 当在存储器和I / O接口之间传输数据时，每个I / O接口都具有一个控制功能来跳过存储器中的一部分区域。

公开(公告)号：US07953292B2

公开(公告)日：2011-05-31

申请号：US11869947

申请日：2007-10-10

申请人： Kazuhiro Hirade

发明人： Kazuhiro Hirade

IPC分类号： G06K9/40

CPC分类号： G06T5/006 ,  G06T3/0018

摘要： An image captured from a camera is subjected to distortion correction processing performed in real time with high accuracy at low cost and is rendered as a smooth image. The image captured from the camera via a capture circuit is stored in a frame memory of a rendering memory unit, and is then subjected to image correction processing by a rendering processing unit. The rendering processing unit adds control points to the image based on distortion information stored in a correction information storing unit, and performs processing so that a shape of a mesh region formed when the control points of the image are connected to one another becomes square by moving the control points. This processing is corrected using, for example, a bilinear filter and the like.

摘要翻译： 从相机拍摄的图像以低成本以高精度实时进行失真校正处理，并且被形成为平滑图像。 通过捕获电路从相机捕获的图像被存储在渲染存储器单元的帧存储器中，然后由渲染处理单元进行图像校正处理。 渲染处理单元基于存储在校正信息存储单元中的失真信息将控制点添加到图像，并且执行处理，使得当图像的控制点彼此连接时形成的网格区域的形状通过移动而成为正方形 控制点。 该处理使用例如双线性滤波器等进行校正。