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1.发明授权Semiconductor device supporting integrated data transfer bridging between CPU memory and I/O device 有权半导体器件支持CPU内存和I / O设备之间的集成数据传输桥接公开(公告)号：US06697906B1
公开(公告)日：2004-02-24
申请号：US09561340
申请日：2000-04-28
申请人： Kazushige Ayukawa , Jun Sato , Takashi Miyamoto , Kenichiro Omura , Hiroyuki Hamasaki , Hiroshi Takeda , Makoto Takano , Isamu Mochizuki , Yasuhiko Hoshi , Kazuhiro Hirade , Ryuichi Murashima
发明人： Kazushige Ayukawa , Jun Sato , Takashi Miyamoto , Kenichiro Omura , Hiroyuki Hamasaki , Hiroshi Takeda , Makoto Takano , Isamu Mochizuki , Yasuhiko Hoshi , Kazuhiro Hirade , Ryuichi Murashima
IPC分类号： G06F100
CPC分类号： G06F13/4031
摘要： A semiconductor device is connected to a CPU, a memory and I/O devices to serve as a data transfer bridge for efficient data transfer between the memory and the I/O devices. A CPU interface and a plurality of I/O interfaces included in a bridge chip are connected through an internal bus to a memory interface included in the bridge chip. Each I/O interface has a read/write buffer and a DMAC. An arbiter included in the bridge chip determines a bus master for which data transfer is permitted in response to requests for data transfer from each of the CPU interface and the DMAC to the memory. Each of the I/O interfaces has a control function to skip part of areas in the memory when transferring data between the memory and the I/O interface.
摘要翻译： 半导体器件连接到CPU，存储器和I / O设备以用作用于在存储器和I / O设备之间进行有效数据传输的数据传输桥。 包括在桥芯片中的CPU接口和多个I / O接口通过内部总线连接到包括在桥芯片中的存储器接口。 每个I / O接口都有一个读/写缓冲区和一个DMAC。 包括在桥芯片中的仲裁器确定响应于从CPU接口和DMAC到存储器的数据传输的请求而允许数据传输的总线主机。 当在存储器和I / O接口之间传输数据时，每个I / O接口都具有一个控制功能来跳过存储器中的一部分区域。
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公开(公告)号：US07868892B2
公开(公告)日：2011-01-11
申请号：US12237112
申请日：2008-09-24
CPC分类号： G06T11/203 , G06T1/20
摘要： An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.
摘要翻译： 本发明的一个目的是提高图形数据处理器中用于绘制和显示控制的控制信息，图形数据等的传送效率。 图形数据处理器包括：CPU; 耦合到CPU的第一个总线; 用于使用第一总线控制数据传输的DMAC; 用于向/从第一总线发送/接收数据的总线桥电路; 三维图形模块，用于经由第一总线从CPU接收命令并执行三维图形处理; 耦合到总线桥电路的第二总线和多个第一电路模块; 耦合到总线桥电路和第二电路模块的第三总线; 以及耦合到第一和第二总线和三维图形模块并且可连接到外部存储器的存储器接口电路，其中总线桥电路可以控制外部电路和第二总线之间的直接存储器访问传输。
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公开(公告)号：US20050030311A1
公开(公告)日：2005-02-10
申请号：US10891047
申请日：2004-07-15
CPC分类号： G06T11/203 , G06T1/20
摘要： An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.
摘要翻译： 本发明的一个目的是提高图形数据处理器中绘图和显示控制的控制信息，图形数据等的传送效率。 图形数据处理器包括：CPU; 耦合到CPU的第一个总线; 用于使用第一总线控制数据传输的DMAC; 用于向/从第一总线发送/接收数据的总线桥电路; 三维图形模块，用于经由第一总线从CPU接收命令并执行三维图形处理; 耦合到总线桥电路的第二总线和多个第一电路模块; 耦合到总线桥电路和第二电路模块的第三总线; 以及耦合到第一和第二总线和三维图形模块并且可连接到外部存储器的存储器接口电路，其中总线桥电路可以控制外部电路和第二总线之间的直接存储器访问传输。
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公开(公告)号：US07446775B2
公开(公告)日：2008-11-04
申请号：US10891047
申请日：2004-07-15
CPC分类号： G06T11/203 , G06T1/20
摘要： An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.
摘要翻译： 本发明的一个目的是提高图形数据处理器中绘图和显示控制的控制信息，图形数据等的传送效率。 图形数据处理器包括：CPU; 耦合到CPU的第一个总线; 用于使用第一总线控制数据传输的DMAC; 用于向/从第一总线发送/接收数据的总线桥电路; 三维图形模块，用于经由第一总线从CPU接收命令并执行三维图形处理; 耦合到总线桥电路的第二总线和多个第一电路模块; 耦合到总线桥电路和第二电路模块的第三总线; 以及耦合到第一和第二总线和三维图形模块并且可连接到外部存储器的存储器接口电路，其中总线桥电路可以控制外部电路和第二总线之间的直接存储器访问传输。
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公开(公告)号：US20090015590A1
公开(公告)日：2009-01-15
申请号：US12237112
申请日：2008-09-24
IPC分类号： G06T15/00
CPC分类号： G06T11/203 , G06T1/20
摘要： An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.
摘要翻译： 本发明的一个目的是提高图形数据处理器中绘图和显示控制的控制信息，图形数据等的传送效率。 图形数据处理器包括：CPU; 耦合到CPU的第一个总线; 用于使用第一总线控制数据传输的DMAC; 用于向/从第一总线发送/接收数据的总线桥电路; 三维图形模块，用于经由第一总线从CPU接收命令并执行三维图形处理; 耦合到总线桥电路的第二总线和多个第一电路模块; 耦合到总线桥电路和第二电路模块的第三总线; 以及耦合到第一和第二总线和三维图形模块并且可连接到外部存储器的存储器接口电路，其中总线桥电路可以控制外部电路和第二总线之间的直接存储器访问传输。
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公开(公告)号：US5070473A
公开(公告)日：1991-12-03
申请号：US77442
申请日：1987-07-24
申请人： Makoto Takano , Yasuhiko Hoshi , Keiichi Kurakazu , Shiro Baba
发明人： Makoto Takano , Yasuhiko Hoshi , Keiichi Kurakazu , Shiro Baba
CPC分类号： G06F13/4213
摘要： A wait signal formed by a program wait circuit incorporated in a microprocessor is transmitted to outside circuitry, such as a slave microprocessor or a direct memory access control device. Thereby an outside device assumes the functions of bus master which is incorporated into a wait operation for access to a memory unit. With such a construction, a microcomputer system comprising a plurality of devices to be made into a bus mask can be simplified.
摘要翻译： 由并入微处理器的程序等待电路形成的等待信号被发送到诸如从微处理器或直接存储器存取控制装置的外部电路。 因此，外部设备承担总线主控器的功能，其被并入到用于访问存储器单元的等待操作中。 通过这样的结构，可以简化包括要制成总线掩模的多个装置的微计算机系统。
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公开(公告)号：US09203217B2
公开(公告)日：2015-12-01
申请号：US14123803
申请日：2012-10-26
申请人： Makoto Takano
发明人： Makoto Takano
IPC分类号： H02B1/04 , H05K7/06 , B62B3/00 , H02M7/48 , H02B1/015 , H05K7/14 , H05K7/20 , H05K5/02 , H02B3/00 , H02M7/00
CPC分类号： H02B1/04 , B62B3/002 , H02B1/015 , H02B3/00 , H02M7/003 , H02M7/48 , H05K7/06 , H05K7/1432 , H05K7/20909
摘要： An inverter apparatus includes an inverter stack having casters at bottom and a switchboard for entering the inverter stack from a front side to store. The switchboard has an output relay terminal, at a storage bottom portion to store the inverter stack, extending along an entering direction of the inverter stack. The output relay terminal is attached with an output electric wire connected to a load at a rear end portion, is connected to an output terminal of the inverter stack at a front end portion, and is fastened to an output relay bar protruding downward from the bottom of the inverter stack through a fastening member.
摘要翻译： 逆变器装置包括在底部具有脚轮的逆变器堆叠和用于从前侧进入逆变器堆叠以存储的配电板。 配电板具有输出继电器端子，在存储底部存储逆变器堆叠，沿反向堆叠的进入方向延伸。 输出继电器端子附接有与后端部的负载连接的输出电线，在前端部连接到逆变器堆叠的输出端子，并且被固定到从底部向下突出的输出继电器棒 的逆变器堆叠通过紧固构件。
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公开(公告)号：US20060291811A1
公开(公告)日：2006-12-28
申请号：US10596607
申请日：2004-12-14
申请人： Yousuke Suzuki , Takahiro Nagai , Makoto Takano
发明人： Yousuke Suzuki , Takahiro Nagai , Makoto Takano
IPC分类号： H04N7/00
CPC分类号： H04N21/472 , H04N7/17318
摘要： When a server device records a portion of a movie after a client device has started a streaming playback, the client device is allowed to make a special playback of that movie. The server device includes: a video recording processing section for recording a movie and generating movie data, made up of predetermined data units, and management information in which a playback duration and a data size are associated with each other for each unit; a storage medium to store the movie data and management information; a receiving section, which receives a request to get the management information and a request to transmit the data unit from the client device; a request processing section for reading the management information and data unit in response to the requests and instructing their transmission; and a transmitting section for transmitting them. If the request to transmit has been received after the management information was transmitted, the request processing section instructs that at least a piece of the newest management information be transmitted with the unit selected by the request to transmit.
摘要翻译： 当服务器设备在客户端设备开始流播放之后记录电影的一部分时，客户端设备被允许对该电影进行特殊播放。 服务器装置包括：用于记录电影并生成由预定数据单元组成的电影数据的视频记录处理部分，以及每个单元对其重放持续时间和数据大小相关联的管理信息; 用于存储电影数据和管理信息的存储介质; 接收部分，其接收获取管理信息的请求和从客户端设备发送数据单元的请求; 请求处理部分，用于响应于请求读取管理信息和数据单元并指示其传送; 以及发送部。 如果在发送管理信息之后已经接收到要发送的请求，则请求处理部分指示用要发送的请求选择的单元发送至少一条最新的管理信息。
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公开(公告)号：US20120113226A1
公开(公告)日：2012-05-10
申请号：US13287129
申请日：2011-11-02
申请人： Keisuke Nakata , Makoto Takano
发明人： Keisuke Nakata , Makoto Takano
CPC分类号： H04N13/128 , H04N13/183 , H04N13/356
摘要： A 3D imaging device is provided that includes an identification unit, a parallax information decision unit, a display position decision unit, and a 3D display control unit. The identification unit calculates parallax information with respect to an object image based on a first image signal and a second image signal. The identification unit also sets identification information for identifying an object image. The identification unit further outputs first parallax information and identification information. The parallax information decision unit decides on second parallax information based on first parallax information so that identification information is visually recognizable at a depth separate from the object image. The 3D display control unit is coupled to at least one of the identification unit, the parallax information decision unit, and the display position decision unit. The 3D display control unit displays identification information superimposed on the first second image signals based on second parallax information.
摘要翻译： 提供了一种3D成像装置，其包括识别单元，视差信息决定单元，显示位置决定单元和3D显示控制单元。 识别单元基于第一图像信号和第二图像信号来计算关于对象图像的视差信息。 识别单元还设置用于识别对象图像的识别信息。 识别单元还输出第一视差信息和识别信息。 视差信息判定单元基于第一视差信息来决定第二视差信息，使得识别信息在与对象图像分离的深度可视觉识别。 3D显示控制单元耦合到识别单元，视差信息决定单元和显示位置决定单元中的至少一个。 3D显示控制单元基于第二视差信息显示叠加在第一第二图像信号上的识别信息。
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10.发明授权公开(公告)号：US07715198B2
公开(公告)日：2010-05-11
申请号：US11798820
申请日：2007-05-17
申请人： Kazuaki Mori , Makoto Takano
发明人： Kazuaki Mori , Makoto Takano
CPC分类号： H02M7/003 , H05K7/1432
摘要： A package structure of an inverter apparatus includes at least four metal column supports arranged vertically to be spaced apart from each other, and sheet-metal bent beams connecting the column supports in transverse direction and longitudinal direction to form rectangular package structure. The metal column support is an aluminum die-cast support, and the sheet-metal bent beam has a U-shape with sharp edges in cross section.
摘要翻译： 逆变器装置的封装结构包括至少四个彼此间隔开地垂直布置的金属柱支撑件，以及在横向和纵向方向上连接柱支撑件的金属板弯曲梁，以形成矩形封装结构。 金属柱支撑件是铝压铸支撑件，并且金属板弯曲梁具有横截面为锐边的U形。
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