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143 条记录 (耗时 0.042 秒)

    Modulating method, modulating device and demodulating device
    1.
    发明授权
    Modulating method, modulating device and demodulating device 失效
    调制方式，调制装置和解调装置

    公开(公告)号：US5506581A

    公开(公告)日：1996-04-09

    申请号：US147836

    申请日：1993-11-05

    申请人： Hiroyuki Ino ,  Takashi Sato ,  Toshiyuki Nakagawa

    发明人： Hiroyuki Ino ,  Takashi Sato ,  Toshiyuki Nakagawa

    IPC分类号： G11B20/14 ,  H03M5/06 ,  H03M5/14 ,  H03M7/14 ,  H04L25/49 ,  H03M7/00

    CPC分类号： H03M5/145 ,  H04L25/4915 ,  G11B20/1426

    摘要： A modulating method, a modulating device and a demodulating device, in which it is possible to improve the digital sum value (DSV) of the coded information, modulated for transmission or recording on the recording medium, are disclosed. An encoding circuit 11 translates a sequence of input data into a sequence of coded data suitable for transmission. A pattern generating circuit 12 generates a pattern of a pre-set length at a pre-set interval inversely proportionate to the low-range cut-off frequency of the modulated coded data. A pattern inserting circuit 13 inserts the patterns into the sequence of coded data A at the pre-set interval. A modulating circuit 14 NRZI modulates the pattern-interlaced sequence of the coded data B and outputs the resulting sequence. A timing control circuit 15 controls the pattern inserting circuit 13 an so forth. The DSV of the modulated coded data may be controlled by the inserted patterns, while the increase in redundancy may be maintained at a necessary minimum value to adapt the DSV control characteristics to the specifications demanded by the transmission system.

    摘要翻译： 公开了一种调制方法，调制装置和解调装置，其中可以改善在记录介质上进行调制以便传输或记录的编码信息的数字和值（DSV）。 编码电路11将输入数据序列转换为适合于传输的编码数据序列。 模式生成电路12以与调制编码数据的低范围截止频率成反比的预设间隔生成预置长度的模式。 模式插入电路13以预设的间隔将模式插入到编码数据A的序列中。 调制电路14 NRZI调制编码数据B的模式隔行序列并输出所得到的序列。 定时控制电路15控制图案插入电路13等。 调制编码数据的DSV可以通过插入的模式进行控制，而冗余度的增加可以保持在必要的最小值，以使DSV控制特性适应于传输系统要求的规范。

    Synchronization signal detector, synchronization signal detecting method and demodulator
    3.
    发明授权
    Synchronization signal detector, synchronization signal detecting method and demodulator 失效
    同步信号检测器，同步信号检测方法和解调器

    公开(公告)号：US5537422A

    公开(公告)日：1996-07-16

    申请号：US565620

    申请日：1995-11-22

    申请人： Yoshihide Shimpuku ,  Hiroyuki Ino ,  Yasuyuki Chaki ,  Toshiyuki Nakagawa

    发明人： Yoshihide Shimpuku ,  Hiroyuki Ino ,  Yasuyuki Chaki ,  Toshiyuki Nakagawa

    IPC分类号： G11B20/12 ,  G11B20/14 ,  G11B27/30 ,  H03M5/06 ,  H03M7/14 ,  H03M7/40 ,  H03M13/00

    CPC分类号： G11B20/1403 ,  G11B20/1426 ,  G11B27/3027 ,  G11B20/1217 ,  G11B2220/2545

    摘要： A synchronization detector includes a NRZI circuit for extracting edge portions of RF signals detected as binary-valued signals to form a pulse train, a counter for counting the number of channel clocks in the distance between transitions represented by the edge portions, a latch circuit operated responsive to pulses from the NRZI circuit for holding a number of previously counted channel clocks immediately preceding a current count of channel clocks, and AND gates and an OR gate for detecting synchronization signals when the combination of the channel clocks from the counter and the latch circuit is the combination of the maximum distance between transitions Tmax and Tmax-kT (k=1 or 2) of a (d, k; m, n; r) modulation code. Synchronization signals may be detected promptly even if the frame structure is increased in size to enable restoration of synchronization to be expedited when frame structure synchronization is not in order. A demodulator utilizing the synchronization signal detector is also disclosed.

    摘要翻译： 同步检测器包括：NRZI电路，用于提取被检测为二进制值信号的RF信号的边缘部分以形成脉冲序列;计数器，用于计数由边缘部分表示的跃迁之间的距离的信道时钟数;锁存电路， 响应于来自NRZI电路的脉冲，用于保持紧邻当前通道时钟计数之前的多个先前计数的通道时钟;以及与门和用于检测同步信号的或门，当来自计数器和锁存电路的通道时钟的组合 是（d，k; m，n; r）调制码的转换Tmax和Tmax-kT（k = 1或2）之间的最大距离的组合。 即使框架结构的大小增加，也可以及时检测同步信号，以便在帧结构同步不顺序时能够恢复同步。 还公开了利用同步信号检测器的解调器。

    Modulating method
    4.
    发明授权
    Modulating method 失效
    调制方式

    公开(公告)号：US5432799A

    公开(公告)日：1995-07-11

    申请号：US64764

    申请日：1993-05-19

    申请人： Yoshihide Shimpuku ,  Hiroyuki Ino ,  Yasuyuki Chaki ,  Toshiyuki Nakagawa

    发明人： Yoshihide Shimpuku ,  Hiroyuki Ino ,  Yasuyuki Chaki ,  Toshiyuki Nakagawa

    IPC分类号： G11B7/00 ,  G11B7/004 ,  G11B7/0045 ,  G11B20/14 ,  H03M7/46 ,  H03M13/00

    CPC分类号： G11B20/1426

    摘要： A method of modulating digital data to a variable-length code having parameters d, k, m, n, and r for recording information on and reproducing the same from an optical disc. The optimal range of a minimum run length d corresponding to the minimum number of successive same symbols is determined by a procedure which includes a first step to determine the minimum S/N required for obtaining a desired error rate from the relationship between a bit error rate and the S/N when d=0; a second step to obtain the relationship between a change of the numerical value d and that of the S/N by calculating, on the basis of the required minimum S/N obtained at the first step, the S/N loss caused due to the change of the numerical value d; and a third step to determine, from the relationship between the numerical value d and the S/N, the range of the value d corresponding to the S/N of the transmission characteristic dependent on an optical system and an optical disc.

    摘要翻译： 将数字数据调制为具有参数d，k，m，n和r的可变长度代码的方法，用于从光盘记录信息并从光盘再现信息。 对应于连续相同符号的最小数量的最小游程长度d的最佳范围由包括第一步骤的步骤来确定，该步骤确定从误码率之间的关系中获得期望误码率所需的最小S / N 当d = 0时S / N; 通过基于在第一步骤中获得的所需最小S / N计算由于第一步骤所产生的S / N损失而获得数值d与S / N的变化之间的关系的第二步骤 数值变化d; 以及第三步骤，根据数值d和S / N之间的关系，确定与取决于光学系统和光盘的传输特性的S / N相对应的值d的范围。

    Data modulating method and apparatus and data demodulating method and apparatus
    5.
    发明授权
    Data modulating method and apparatus and data demodulating method and apparatus 失效
    数据调制方法及装置及数据解调方法及装置

    公开(公告)号：US5355133A

    公开(公告)日：1994-10-11

    申请号：US15477

    申请日：1993-02-09

    申请人： Yoshihide Shimpuku ,  Hiroyuki Ino ,  Yasuyuki Chaki ,  Toshiyuki Nakagawa

    发明人： Yoshihide Shimpuku ,  Hiroyuki Ino ,  Yasuyuki Chaki ,  Toshiyuki Nakagawa

    IPC分类号： G11B20/14 ,  H03M5/14 ,  H03M7/40 ,  H03M5/18

    CPC分类号： G11B20/1426 ,  H03M5/145

    摘要： A modulating method and apparatus and a demodulating method and apparatus wherein high density recording can be achieved and a dc component can be controlled with a variable length channel code are disclosed. Recording data are divided into a predetermined plurality of blocks, and those of the recording data at a portion other than a boundary portion of each of the blocks are coded referring to a table of a first ROM so that data of m bits may be converted into a code of n bits. The remaining data at the boundary portion of each block are converted into a code referring to another table of second ROM so that data of m bits may be converted into a code of n bits. Further, a code of n bits for minimizing a dc component is produced referring to a third table of a further ROM and is added to the code generated by the first and second ROMs.

    摘要翻译： 公开了可以实现高密度记录并且可以用可变长度信道码来控制直流分量的调制方法和装置以及解调方法和装置。 记录数据被划分为预定的多个块，并且在每个块的边界部分之外的部分处的记录数据的那些被编码，参考第一ROM的表，使得m位的数据可以被转换成 n位的代码。 每个块的边界部分的剩余数据被转换成参考第二ROM的另一个表的代码，使得m位的数据可以被转换成n位的代码。 此外，参考另一ROM的第三表产生用于最小化直流分量的n位的代码，并将其添加到由第一和第二ROM产生的代码中。

    Data decoder
    9.
    发明授权
    Data decoder 失效
    数据解码器

    公开(公告)号：US6111833A

    公开(公告)日：2000-08-29

    申请号：US930162

    申请日：1997-10-03

    申请人： Toshiyuki Nakagawa ,  Hiroyuki Ino ,  Shunji Yoshimura ,  Shinichi Kai

    发明人： Toshiyuki Nakagawa ,  Hiroyuki Ino ,  Shunji Yoshimura ,  Shinichi Kai

    IPC分类号： G11B20/10 ,  G11B20/14 ,  G11B20/18 ,  H03M5/14 ,  H04L25/49 ,  G11B7/00

    CPC分类号： H04L25/4906 ,  G11B20/10009 ,  G11B20/1426 ,  G11B20/18 ,  H03M5/145

    摘要： In a data decoding apparatus of this invention, level of a reproduction RF signal 7a at the time of the binary level judgment of channel bit is temporarily stored into a RF signal level memory section 20. The portions which do not satisfy the conditions of the minimum run length and the maximum run length of the same symbols within the channel bit data train are respectively detected by a (d'-1) detecting section 16 and a (k'+1) detecting section 17. This data decoding apparatus comprises correction bit position detecting sections 18, 19 for outputting correction bit position designation signals on the basis of level of the RF signal at the time of the binary level judgment stored in the RF signal level memory section 20, and a bit data inversion correcting section 15 for inverting logic level of data at bit position designated on the basis of the correction bit position designation signals 18a, 18b, 19a, 19b. In the case where there exists any portion which does not satisfy the conditions of the minimum run length and/or the maximum run length of the same symbols within channel bit data obtained by binarizing a signal which has been read out from the recording medium, correction is implemented to the channel bit data, thereby making it possible to improve the bit error rate, and to ensure skew margin.

    摘要翻译： PCT No.PCT / JP97 / 00336 Sec。 371日期1997年10月3日第 102（e）日期1997年10月3日PCT 1997年2月7日提交PCT公布。 WO97 / 29485 PCT公开号 日期：1997年8月14日在本发明的数据解码装置中，通道位的二进制判定时的再现RF信号7a的电平临时存储到RF信号电平存储部20中。不满足的部分 信道位数据序列中相同符号的最小游程长度和最大游程长度的条件分别由（d'-1）检测部分16和（k'+ 1）检测部分17检测。该数据 解码装置包括校正位位置检测部分18,19，用于根据存储在RF信号电平存储部分20中的二进制电平判断时的RF信号的电平输出校正位位置指定信号，以及位数据反转 校正部分15，用于反转基于校正位位置指定信号18a，18b，19a，19b指定的比特位置的数据的逻辑电平。 在通过对从记录介质读出的信号进行二值化获得的通道位数据中存在不满足最小游程长度的条件和/或相同符号的最大游程长度的部分的情况下， 被实现到通道位数据，从而使得可以提高误码率，并且确保倾斜余量。