公开(公告)号：US20070285907A1

公开(公告)日：2007-12-13

申请号：US11836637

申请日：2007-08-09

申请人： Hiroyuki NISHIKAWA ,  Shigeo TANAHASHI ,  Katsura HAYASHI

发明人： Hiroyuki NISHIKAWA ,  Shigeo TANAHASHI ,  Katsura HAYASHI

IPC分类号： H05K1/18

CPC分类号： H05K1/185 ,  H01L23/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/183 ,  H05K3/4602 ,  H05K3/4697 ,  H01L2224/05599

摘要： There is disclosed a wiring board comprising a core substrate 110, a build-up layer 130a formed on at least one side of main surfaces the core substrate, wherein a cavity 120 for accommodating a chip-type decoupling capacitor 121 is formed in the build-up layer 130a. The capacitor 121 includes electrode terminals on an upper surface thereof that are directly connected to a semiconductor component, and electrode terminals on a back surface of the capacitor 121 is connected to a wiring conductor layer 132a on a bottom surface of the cavity 120. This structure enables decoupling capacitor and the semiconductor component 260 to be connected with low resistance and low inductance.

摘要翻译： 公开了一种布线板，其包括芯基板110，形成在芯基板的主表面的至少一侧上的堆积层130a，其中在构造中形成用于容纳芯片型去耦电容器121的空腔120 上层130a。 电容器121包括其上表面上直接连接到半导体部件的电极端子，并且电容器121的背面上的电极端子连接到空腔120的底表面上的布线导体层132a。 该结构使得去耦电容器和半导体部件260能够连接低电阻和低电感。