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    METHOD FOR SEMICONDUCTOR CIRCUIT
    1.
    发明申请
    METHOD FOR SEMICONDUCTOR CIRCUIT 失效
    半导体电路方法

    公开(公告)号：US20090132974A1

    公开(公告)日：2009-05-21

    申请号：US12024107

    申请日：2008-01-31

    申请人： Hiroyuki YOSHIMOTO ,  Nobuyuki Sugii ,  Shinichi Saito ,  Digh Hisamoto

    发明人： Hiroyuki YOSHIMOTO ,  Nobuyuki Sugii ,  Shinichi Saito ,  Digh Hisamoto

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： Capacity-gate voltage characteristics of a field-effect transistor having plural gates are measured against a voltage change in each one of the gates for an inverted MOSFET and for an accumulated MOSFET, respectively. These measurements together with numerical simulations provided from a model for quantum effects are used to determine flat band voltages between the plural gates and a channel. Next, an effective normal electric field is calculated as a vector line integral by using a set of flat band voltages for the measured capacity as a lower integration limit. Lastly, mobility depending on the effective normal electric field is calculated from current-gate voltage characteristic measurements and capacity measurements in a source-drain path, and the calculated mobility is substituted into an equation for a current-voltage curve between source and drain.

    摘要翻译： 针对反向MOSFET的栅极和积累的MOSFET中的每一个的电压变化分别测量具有多个栅极的场效应晶体管的容量栅极电压特性。 这些测量结果与从量子效应模型提供的数值模拟一起用于确定多个门和通道之间的平带电压。 接下来，通过使用一组用于测量容量的平带电压作为下积分极限，计算有效正常电场作为矢量线积分。 最后，根据源极 - 漏极路径中的电流 - 栅极电压特性测量和电容测量值计算出有效正常电场的迁移率，并将计算的迁移率代入源极和漏极之间的电流 - 电压曲线的方程式。

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20100258872A1

    公开(公告)日：2010-10-14

    申请号：US12756451

    申请日：2010-04-08

    申请人： Nobuyuki SUGII ,  Ryuta TSUCHIYA ,  Shinichiro KIMURA ,  Takashi ISHIGAKI ,  Yusuke MORITA ,  Hiroyuki YOSHIMOTO

    发明人： Nobuyuki SUGII ,  Ryuta TSUCHIYA ,  Shinichiro KIMURA ,  Takashi ISHIGAKI ,  Yusuke MORITA ,  Hiroyuki YOSHIMOTO

    IPC分类号： H01L29/786 ,  H01L27/12

    CPC分类号： H01L27/1203 ,  H01L21/76283

    摘要： A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.

    摘要翻译： 通过改善在SOI衬底的浅沟槽和SOI层的边界部分的形状来实现低功耗的半导体器件的技术。 硅衬底的主表面和沿着SOI层的侧表面延伸的线交叉的位置（SOI边缘）比浅沟槽隔离更远离位于（STI边缘）的位置（STI边缘），在该位置处 沿着浅沟槽的侧壁延伸并且沿着硅衬底的主表面延伸的线交叉，并且在STI边缘处的硅衬底的拐角具有弯曲表面。