公开(公告)号：US07890898B2

公开(公告)日：2011-02-15

申请号：US12024107

申请日：2008-01-31

申请人： Hiroyuki Yoshimoto ,  Nobuyuki Sugii ,  Shinichi Saito ,  Digh Hisamoto

发明人： Hiroyuki Yoshimoto ,  Nobuyuki Sugii ,  Shinichi Saito ,  Digh Hisamoto

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Capacity-gate voltage characteristics of a field-effect transistor having plural gates are measured against a voltage change in each one of the gates for an inverted MOSFET and for an accumulated MOSFET, respectively. These measurements together with numerical simulations provided from a model for quantum effects are used to determine flat band voltages between the plural gates and a channel. Next, an effective normal electric field is calculated as a vector line integral by using a set of flat band voltages for the measured capacity as a lower integration limit. Lastly, mobility depending on the effective normal electric field is calculated from current-gate voltage characteristic measurements and capacity measurements in a source-drain path, and the calculated mobility is substituted into an equation for a current-voltage curve between source and drain.

摘要翻译： 针对反向MOSFET的栅极和积累的MOSFET中的每一个的电压变化分别测量具有多个栅极的场效应晶体管的容量栅极电压特性。 这些测量结果与从量子效应模型提供的数值模拟一起用于确定多个门和通道之间的平带电压。 接下来，通过使用一组用于测量容量的平带电压作为下积分极限，计算有效正常电场作为矢量线积分。 最后，根据源极 - 漏极路径中的电流 - 栅极电压特性测量和电容测量值计算出有效正常电场的迁移率，并将计算的迁移率代入源极和漏极之间的电流 - 电压曲线的方程式。

公开(公告)号：US20090132974A1

公开(公告)日：2009-05-21

申请号：US12024107

申请日：2008-01-31

申请人： Hiroyuki YOSHIMOTO ,  Nobuyuki Sugii ,  Shinichi Saito ,  Digh Hisamoto

发明人： Hiroyuki YOSHIMOTO ,  Nobuyuki Sugii ,  Shinichi Saito ,  Digh Hisamoto

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Capacity-gate voltage characteristics of a field-effect transistor having plural gates are measured against a voltage change in each one of the gates for an inverted MOSFET and for an accumulated MOSFET, respectively. These measurements together with numerical simulations provided from a model for quantum effects are used to determine flat band voltages between the plural gates and a channel. Next, an effective normal electric field is calculated as a vector line integral by using a set of flat band voltages for the measured capacity as a lower integration limit. Lastly, mobility depending on the effective normal electric field is calculated from current-gate voltage characteristic measurements and capacity measurements in a source-drain path, and the calculated mobility is substituted into an equation for a current-voltage curve between source and drain.

摘要翻译： 针对反向MOSFET的栅极和积累的MOSFET中的每一个的电压变化分别测量具有多个栅极的场效应晶体管的容量栅极电压特性。 这些测量结果与从量子效应模型提供的数值模拟一起用于确定多个门和通道之间的平带电压。 接下来，通过使用一组用于测量容量的平带电压作为下积分极限，计算有效正常电场作为矢量线积分。 最后，根据源极 - 漏极路径中的电流 - 栅极电压特性测量和电容测量值计算出有效正常电场的迁移率，并将计算的迁移率代入源极和漏极之间的电流 - 电压曲线的方程式。

公开(公告)号：US07812398B2

公开(公告)日：2010-10-12

申请号：US12400324

申请日：2009-03-09

申请人： Shinichi Saito ,  Digh Hisamoto ,  Yoshinobu Kimura ,  Nobuyuki Sugii ,  Ryuta Tsuchiya

发明人： Shinichi Saito ,  Digh Hisamoto ,  Yoshinobu Kimura ,  Nobuyuki Sugii ,  Ryuta Tsuchiya

IPC分类号： H01L27/01 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/7846 ,  H01L29/785

摘要： A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.

摘要翻译： 提供了一种半导体器件及其制造方法，其中通过使用现有的硅工艺容易地形成的方案，增加了pMOSFET的驱动电流。 在（100）硅衬底上形成具有<100>方向的沟道的pMOSFET。 通过STI在垂直于通道的方向上施加压应力。

公开(公告)号：US20070284582A1

公开(公告)日：2007-12-13

申请号：US11746230

申请日：2007-05-09

申请人： SHINICHI SAITO ,  Digh Hisamoto ,  Yoshinobu Kimura ,  Nobuyuki Sugii ,  Ryuta Tsuchiya

发明人： SHINICHI SAITO ,  Digh Hisamoto ,  Yoshinobu Kimura ,  Nobuyuki Sugii ,  Ryuta Tsuchiya

IPC分类号： H01L29/76

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/7846 ,  H01L29/785

摘要： A semiconductor device and manufacturing method of the same is provided in which the driving current of a PMOSFET is increased, through a scheme formed easily using an existing silicon process. A PMOSFET is formed with a channel in a direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.

摘要翻译： 提供了一种半导体器件及其制造方法，其中通过使用现有的硅工艺容易地形成的方案，PMOSFET的驱动电流增加。 在（100）硅衬底上形成具有沿<100>方向的沟道的PMOSFET。 通过STI在垂直于通道的方向上施加压应力。

公开(公告)号：US07531853B2

公开(公告)日：2009-05-12

申请号：US11746230

申请日：2007-05-09

申请人： Shinichi Saito ,  Digh Hisamoto ,  Yoshinobu Kimura ,  Nobuyuki Sugii ,  Ryuta Tsuchiya

发明人： Shinichi Saito ,  Digh Hisamoto ,  Yoshinobu Kimura ,  Nobuyuki Sugii ,  Ryuta Tsuchiya

IPC分类号： H01L29/80 ,  H01L31/112 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045 ,  H01L29/7846 ,  H01L29/785

摘要： A semiconductor device and manufacturing method of the same is provided in which the driving current of a pMOSFET is increased, through a scheme formed easily using an existing silicon process. A pMOSFET is formed with a channel in a direction on a (100) silicon substrate. A compressive stress is applied in a direction perpendicular to the channel by an STI.

摘要翻译： 提供了一种半导体器件及其制造方法，其中通过使用现有的硅工艺容易地形成的方案，增加了pMOSFET的驱动电流。 在（100）硅衬底上形成具有<100>方向的沟道的pMOSFET。 通过STI在垂直于通道的方向上施加压应力。

公开(公告)号：US20120018807A1

公开(公告)日：2012-01-26

申请号：US13145108

申请日：2010-01-18

申请人： Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Yusuke Morita ,  Hiroyuki Yoshimoto ,  Takashi Ishigaki ,  Shinichiro Kimura

发明人： Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Yusuke Morita ,  Hiroyuki Yoshimoto ,  Takashi Ishigaki ,  Shinichiro Kimura

IPC分类号： H01L27/12 ,  B82Y99/00

CPC分类号： H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/78648

摘要： In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.

摘要翻译： 在以高功率低功耗工作的SOI-MISFET中，元件面积减小。 虽然SOI型MISFET的N导电型MISFET区域的扩散层区域和SOI型MISFET的P导电型MISFET区域的扩散层区域形成为公共区域，但是施加衬底电位的阱扩散层 通过STI层将N导电型MISFET区域和P导电型MISFET区域相互分离。 位于N和P导电型MISFET区域中的扩散层区域）作为CMISFET的输出部分形成为公共区域，并通过硅化金属直接连接，使元件面积减小。

公开(公告)号：US08183635B2

公开(公告)日：2012-05-22

申请号：US12756451

申请日：2010-04-08

申请人： Nobuyuki Sugii ,  Ryuta Tsuchiya ,  Shinichiro Kimura ,  Takashi Ishigaki ,  Yusuke Morita ,  Hiroyuki Yoshimoto

发明人： Nobuyuki Sugii ,  Ryuta Tsuchiya ,  Shinichiro Kimura ,  Takashi Ishigaki ,  Yusuke Morita ,  Hiroyuki Yoshimoto

IPC分类号： H01L21/00

CPC分类号： H01L27/1203 ,  H01L21/76283

摘要： A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.

摘要翻译： 通过改善在SOI衬底的浅沟槽和SOI层的边界部分的形状来实现低功耗的半导体器件的技术。 硅衬底的主表面和沿着SOI层的侧表面延伸的线交叉的位置（SOI边缘）比浅沟槽隔离更远离位于（STI边缘）的位置（STI边缘），在该位置处 沿着浅沟槽的侧壁延伸并且沿着硅衬底的主表面延伸的线交叉，并且在STI边缘处的硅衬底的拐角具有弯曲表面。

公开(公告)号：US08643117B2

公开(公告)日：2014-02-04

申请号：US13145108

申请日：2010-01-18

申请人： Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Yusuke Morita ,  Hiroyuki Yoshimoto ,  Takashi Ishigaki ,  Shinichiro Kimura

发明人： Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Yusuke Morita ,  Hiroyuki Yoshimoto ,  Takashi Ishigaki ,  Shinichiro Kimura

IPC分类号： H01L21/70

CPC分类号： H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/78648

摘要： In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.

摘要翻译： 在以高功率低功耗工作的SOI-MISFET中，元件面积减小。 虽然SOI型MISFET的N导电型MISFET区域的扩散层区域和SOI型MISFET的P导电型MISFET区域的扩散层区域形成为公共区域，但是施加衬底电位的阱扩散层 通过STI层将N导电型MISFET区域和P导电型MISFET区域相互分离。 位于N和P导电型MISFET区域中的扩散层区域）作为CMISFET的输出部分形成为公共区域，并通过硅化金属直接连接，使元件面积减小。

公开(公告)号：US20100258869A1

公开(公告)日：2010-10-14

申请号：US12757090

申请日：2010-04-09

申请人： Yusuke MORITA ,  Ryuta Tsuchiya ,  Takashi Ishigaki ,  Hiroyuki Yoshimoto ,  Nobuyuki Sugii ,  Shinichiro Kimura

发明人： Yusuke MORITA ,  Ryuta Tsuchiya ,  Takashi Ishigaki ,  Hiroyuki Yoshimoto ,  Nobuyuki Sugii ,  Shinichiro Kimura

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203

摘要： An n well and a p well disposed at a predetermined interval on a main surface of a SOI substrate with a thin BOX layer are formed, and an nMIS formed on the p well has a pair of n-type source/drain regions formed on semiconductor layers stacked on a main surface of the SOI layer at a predetermined distance, a gate insulating film, a gate electrode and sidewalls sandwiched between the pair of n-type source/drain regions. A device isolation is formed between the n well and the p well, and a side edge portion of the device isolation extends toward a gate electrode side more than a side edge portion of the n-type source/drain region (sidewall of the BOX layer).

摘要翻译： 形成在具有薄BOX层的SOI衬底的主表面上以预定间隔布置的n阱和p阱，并且在p阱上形成的nMIS具有形成在半导体层上的一对n型源极/漏极区 堆叠在SOI层的主表面上，预定距离处，栅极绝缘膜，栅电极和夹在该对n型源极/漏极区之间的侧壁。 在n阱和p阱之间形成器件隔离，并且器件隔离的侧边缘部分比n型源极/漏极区域的侧边缘部分（BOX层的侧壁）朝向栅电极侧延伸 ）。

公开(公告)号：US20110227116A1

公开(公告)日：2011-09-22

申请号：US13129115

申请日：2009-10-21

申请人： Shinichi Saito ,  Masahiro Aoki ,  Nobuyuki Sugii ,  Katsuya Oda ,  Toshiki Sugawa

发明人： Shinichi Saito ,  Masahiro Aoki ,  Nobuyuki Sugii ,  Katsuya Oda ,  Toshiki Sugawa

IPC分类号： H01L33/34 ,  H01L33/60 ,  H01L31/028 ,  H01L31/18

CPC分类号： H01S5/3201 ,  H01L31/103 ,  H01L31/1808 ,  H01S5/0208 ,  H01S5/021 ,  H01S5/026 ,  H01S5/0264 ,  H01S5/0424 ,  H01S5/1032 ,  H01S5/1231 ,  H01S5/125 ,  H01S5/3223 ,  Y02E10/50

摘要： An object of the present invention is to provide a germanium laser diode that can be easily formed on a substrate such as silicon by using a normal silicon process and can emit light efficiently. A germanium light-emitting device according to the present invention is a germanium laser diode characterized in that tensile strain is applied to single-crystal germanium serving as a light-emitting layer to be of a direct transition type, a thin semiconductor layer made of silicon, germanium or silicon-germanium is connected adjacently to both ends of the germanium light-emitting layer, the thin semiconductor layer has a certain degree of thickness capable of preventing the occurrence of quantum confinement effect, another end of the thin semiconductor layer is connected to a thick electrode doped with impurities at a high concentration, the electrode is doped to a p type and an n type, a waveguide is formed so as not to be in direct contact with the electrode, and a mirror is formed at an end of the waveguide.

摘要翻译： 本发明的目的是提供一种可以通过使用普通硅工艺容易地在诸如硅的衬底上形成的锗激光二极管，并且能够有效发光。 根据本发明的锗发光器件是锗激光二极管，其特征在于将拉伸应变施加到作为直接转变型的发光层的单晶锗，由硅制成的薄半导体层 ，锗或锗锗与锗发光层的两端相邻连接，薄型半导体层具有能够防止量子限制效应发生的一定程度的厚度，薄半导体层的另一端与 以高浓度掺杂有杂质的厚电极，电极被掺杂成ap型和n型，形成波导以不与电极直接接触，并且在波导的端部形成反射镜 。