公开(公告)号：US06900671B2

公开(公告)日：2005-05-31

申请号：US10325902

申请日：2002-12-23

申请人： Hiroyuki Yamada ,  Shigeyuki Tamura ,  Kuniichi Ikemura

发明人： Hiroyuki Yamada ,  Shigeyuki Tamura ,  Kuniichi Ikemura

IPC分类号： H03F1/34 ,  H03F3/08 ,  H03G3/30 ,  H02M11/00

CPC分类号： H03G3/3084

摘要： It is an object of the present invention to provide a current-voltage conversion circuit in which the sensitivity varies in accordance with the amplitude of the input signal. In the current-voltage conversion circuit of the present invention, n+1 (n is an even number) amplifying inverters are connected in series between an input terminal and an output terminal; furthermore, the input of a negative feedback circuit constructed from an integrating circuit and a negative feedback inverter is connected to the output side of the nth-stage amplifying inverter, and the output of this negative feedback circuit is connected to the input side of the first-stage amplifying inverter. The integrating circuit outputs the mean value of the output potential of the nth-stage amplifying inverter into the negative feedback inverter, and the negative feedback inverter controls the current that flows the ground line from the input terminal in accordance with the output voltage of the integrating circuit. As a result, the sensitivity of the current-voltage conversion circuit varies accordingly.

摘要翻译： 本发明的目的是提供一种电流 - 电压转换电路，其中灵敏度根据输入信号的幅度而变化。 在本发明的电流 - 电压转换电路中，n + 1（n为偶数）放大逆变器串联连接在输入端子和输出端子之间; 此外，由积分电路和负反馈反相器构成的负反馈电路的输入连接到第n阶段放大反相器的输出侧，该负反馈电路的输出为 连接到第一级放大逆变器的输入侧。 积分电路将第n级阶段放大逆变器的输出电位的平均值输出到负反馈反相器，负反馈反相器控制从输入端子流过地线的电流 根据积分电路的输出电压。 结果，电流 - 电压转换电路的灵敏度相应地变化。

公开(公告)号：US06343355B1

公开(公告)日：2002-01-29

申请号：US09261462

申请日：1999-02-24

申请人： Kuniichi Ikemura

发明人： Kuniichi Ikemura

IPC分类号： G06F1206

CPC分类号： G11C8/04

摘要： A sequence controller includes a sequencer to which a basic clock is applied. The sequencer sequentially generates at a period of 125 &mgr;sec address signals for reading statements to be executed at a period of 125 &mgr;sec and one block of statements to be executed at a period of 10 msec or one block of statements to be executed at a period of 100 msec. A memory stores the above statements beforehand. The statements are selectively read out of the memory in accordance with the address signals and fed to a decoder. The decoder decodes the statements and generates control signals respectively corresponding to the statements and feeds the control signals to a switch. The switch controls each of a plurality of function registers on the basis of the respective control signal.

摘要翻译： 序列控制器包括应用基本时钟的定序器。 定序器以125个音频地址信号的周期顺序地生成用于读取要在125个音频周期执行的语句和要在10毫秒的时间段执行的一个语句块，或者在一段期间执行的一个语句块 100毫秒 一个内存预先存储上面的语句。 这些语句根据地址信号被选择性地从存储器中读出并馈送到解码器。 解码器解码语句并产生分别对应于语句的控制信号并将控制信号馈送到开关。 该开关基于相应的控制信号控制多个功能寄存器中的每一个。

公开(公告)号：US5400369A

公开(公告)日：1995-03-21

申请号：US87281

申请日：1993-07-08

申请人： Kuniichi Ikemura

发明人： Kuniichi Ikemura

IPC分类号： H04J3/06 ,  H04L7/08 ,  H04Q11/04 ,  H04L7/00

CPC分类号： H04J3/0608 ,  H04J2203/0089

摘要： A frame aligner detects sync patterns consisting of at least two units of data having a first value followed by at least two units of data having a second value in a serial data signal. The serial signal is demultiplexed to units of parallel data, which are stored in a shift register having a capacity of two units of data. All but one bit off the stored data are scanned to detect a unit having the first value. When such a unit is detected, alignment data indicating its position in the shift register are generated. The alignment data are latched and used to extract subsequent units from the shift register. New and old alignment data are compared to detect aligned units having the first value. A sync pattern is recognized as a consecutive sequence of such aligned units followed by a consecutive sequence of units having the second value.

摘要翻译： 帧对准器检测由具有第一值的至少两个数据单元组成的同步模式，随后是在串行数据信号中具有第二值的至少两个数据单元。 串行信号被解复用为并行数据单元，其被存储在具有两个数据单元的容量的移位寄存器中。 对存储的数据进行除了一个位的扫描，以检测具有第一个值的单元。 当检测到这样的单元时，产生指示其在移位寄存器中的位置的对准数据。 对准数据被锁存并用于从移位寄存器中提取后续单元。 比较新旧对准数据以检测具有第一值的对准单元。 同步模式被识别为这种对齐单元的连续序列，之后是具有第二值的连续的单位序列。