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公开(公告)号：US4888584A
公开(公告)日：1989-12-19
申请号：US273676
申请日：1988-11-21
摘要： A vector pattern processing circuit for a bit map display system including a display unit having a plurality of quasi regions in a matrix form defined in a plane of the display unit each forming N.times.N dots. The circuit includes first and second memory units each including a plurality of words formed in a matrix, each word having an N.times.N bits structure; the words in the first memory unit corresponding to diagonal quasi regions of the display unit and the words in the second memory unit corresponding other diagonal quasi regions; first and second word register units, each having an N.times.N bits structure; a digital differential analyzer (DDA) generating a first dot data of a primary axis for a processing vector pattern and a second dot data of a subsidiary axis perpendicular to the primary axis in response to a gradient of the vector pattern along the primary axis for every N dots in the primary axis. The circuit further includes a bit setting circuit energizing one of the word register units in response to the first and second dot data from the DDA and setting a bit defined by the dot data to the energized word register unit in each dot data generation time at the DDA; and a store control circuit addressing at least one address of a word in one of the memory unit defined by the coordinate, so that at least one of data set in one of the word register units is stored in the word defined by the address.
摘要翻译： 一种用于位图显示系统的矢量图案处理电路，包括：显示单元，该显示单元具有矩阵形式的多个准区域，每个准区域在所述显示单元的平面中形成，每个形成N×N个点。 该电路包括第一和第二存储器单元，每个存储单元包括以矩阵形式形成的多个字，每个字具有N×N位结构; 对应于显示单元的对角准准区域的第一存储单元中的单词和第二存储单元中的对应于其它对角准准区域的单词; 第一和第二字寄存器单元，每个具有N×N位结构; 数字差分分析器（DDA），响应于沿着主轴的矢量图案的梯度，针对每一个，生成用于处理矢量图案的主轴的第一点数据和垂直于主轴的辅轴的第二点数据 主轴上有N个点。 电路还包括位设置电路，响应于来自DDA的第一和第二点数据，激励字寄存器单元中的一个，并且在每个点数据生成时间中将由点数据定义的位设置为通电字寄存器单元 DDA; 以及存储控制电路，寻址由坐标定义的存储器单元之一中的字的至少一个地址，使得在一个字寄存器单元中设置的数据中的至少一个存储在由该地址定义的字中。
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公开(公告)号：US4933879A
公开(公告)日：1990-06-12
申请号：US157231
申请日：1988-02-18
IPC分类号： G11C11/401 , G06F12/00 , G06T1/60 , G09G5/02 , G09G5/393
摘要： A multi-plane video RAM for displaying a color image on a display apparatus. A multi-plane bit operation unit is used for calculating input data from an external stage based on a predetermined rule corresponding to an information applied from the external stage. Memory arrays are operatively connected to the multi-plane bit operation unit for writing resultant data calculated by the multi-plane bit operation unit. Each array having three-dimensionally arranged k sets of memory planes each consisting of m (rows).times.n (columns); wherein the same corresponding positions of the k sets of memory planes are simultaneously accessed and the resultant data calculated by the multi-plane bit operation unit are also simultaneously written thereto.
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公开(公告)号：US5586234A
公开(公告)日：1996-12-17
申请号：US61087
申请日：1993-05-13
CPC分类号： G06T15/04
摘要： A three-dimensional graphic drawing apparatus having texture pattern memory units which store a texture pattern having a set of texture pixel data designated by two-dimensional ST texture coordinate values. A display memory unit writes a two-dimensional image of a surface shape of a three-dimensional object to an address designated by two-dimensional XY display coordinate values corresponding to a display screen. Mapping units produce two-dimensional UV surface shape coordinate values of a three-dimensional object which are projected onto the two-dimensional UV surface shape. The mapping units convert the coordinate values into two-dimensional ST texture coordinate values, read out corresponding texture pixel data designating the two-dimensional XY display coordinate values corresponding to the two-dimensional UV surface shape coordinate values, and write two-dimensional XY display coordinate values into the display memory unit. A parallel processing unit reads texture pixel data from different coordinate positions from the texture pattern memory unit using a single access of the mapping unit when the texture pattern has been stored into the plurality of texture pattern memory units and enables the texture pixel data to be simultaneously written into the display memory unit. A time-division processing unit selects a texture pattern memory unit when different kinds of texture patterns have been stored into the texture pattern memory units, for sequentially reading the texture pixel data by the mapping units and writes out the texture pixel data to be written into the display memory unit.
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4.发明授权
公开(公告)号：US6052126A
公开(公告)日：2000-04-18
申请号：US741355
申请日：1996-10-29
CPC分类号： G06T15/04
摘要： A three-dimensional graphic drawing apparatus having texture pattern memory units which store a texture pattern having a set of texture pixel data designated by two-dimensional ST texture coordinate values. A display memory unit writes a two-dimensional image of a surface shape of a three-dimensional object to an address designated by two-dimensional XY display coordinate values corresponding to a display screen. Mapping units produce two-dimensional UV surface shape coordinate values of a three-dimensional object which are projected onto the two-dimensional UV surface shape. The mapping units convert the coordinate values into two-dimensional ST texture coordinate values, read out corresponding texture pixel data designating the two-dimensional XY display coordinate values corresponding to the two-dimensional UV surface shape coordinate values, and write two-dimensional XY display coordinate values into the display memory unit. A parallel processing unit reads texture pixel data from different coordinate positions from the texture pattern memory unit using a single access of the mapping unit when the texture pattern has been stored into the plurality of texture pattern memory units and enables the texture pixel data to be simultaneously written into the display memory unit. A time-division processing unit selects a texture pattern memory unit when different kinds of texture patterns have been stored into the texture pattern memory units, for sequentially reading the texture pixel data by the mapping units and writes out the texture pixel data to be written into the display memory unit.
摘要翻译： 具有纹理图形存储单元的三维图形绘制装置，其存储具有由二维ST纹理坐标值指定的一组纹理像素数据的纹理图案。 显示存储单元将三维物体的表面形状的二维图像写入由对应于显示屏幕的二维XY显示坐标值指定的地址。 映射单元产生投影在二维UV表面形状上的三维物体的二维UV表面形状坐标值。 映射单元将坐标值转换为二维ST纹理坐标值，读出指定对应于二维UV表面形状坐标值的二维XY显示坐标值的对应纹理像素数据，并写入二维XY显示 将坐标值放入显示存储单元。 当纹理图案已被存储到多个纹理图案存储单元中并且使得纹理像素数据同时被使用时，并行处理单元使用映射单元的单个访问从不同坐标位置从纹理图案存储单元读取纹理像素数据 写入显示存储单元。 时分处理单元在纹理图案存储单元中存储了不同种类的纹理图案时，选择纹理图案存储单元，通过映射单元依次读取纹理像素数据，并写出要写入的纹理像素数据 显示存储单元。
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5.发明授权Three dimensional parallel drawing apparatus for synthesizing graphics data with image data using a pixel depth buffer and an image depth register 失效使用像素深度缓冲器和图像深度寄存器将图形数据与图像数据合成的三维平行绘制装置
公开(公告)号：US5850224A
公开(公告)日：1998-12-15
申请号：US738604
申请日：1996-10-29
申请人： Takahiro Sakuraba
发明人： Takahiro Sakuraba
CPC分类号： G06T15/04
摘要： A three-dimensional graphics drawing apparatus having a plurality of frame buffers, a Z buffer and a Z register. The frame buffers are for writing pixel data into an address designated by coordinate values (X, Y) of ZY display coordinates and for storing an image. The Z buffer is for storing a plurality of coordinate values (Z) indicating a depth direction for each pixel data written by the frame buffer. The Z register is an alternative to the Z buffer and is used for writing a single coordinate value (Z) in place of storing the coordinate value Z for every pixel in the Z buffer, when the coordinate value (Z) in the depth direction of the pixel data stored in the frame buffer have the same value for all of the pixel data. A merge unit is provided for selecting visible pixel data from the plurality of pixel data read from the frame buffer on the basis of the coordinate value (Z) in the Z buffer and the Z register. The merge unit subsequently writes the selected pixel data into a frame buffer for synthesis.
摘要翻译： 具有多个帧缓冲器，Z缓冲器和Z寄存器的三维图形绘制装置。 帧缓冲器用于将像素数据写入由ZY显示坐标的坐标值（X，Y）指定的地址并用于存储图像。 Z缓冲器用于存储指示由帧缓冲器写入的每个像素数据的深度方向的多个坐标值（Z）。 Z寄存器是Z缓冲器的替代，并且用于写入单个坐标值（Z）代替存储Z缓冲器中的每个像素的坐标值Z，当在Z缓冲器的深度方向上的坐标值（Z） 存储在帧缓冲器中的像素数据对于所有像素数据具有相同的值。 提供合并单元，用于基于Z缓冲器和Z寄存器中的坐标值（Z）从从帧缓冲器读取的多个像素数据中选择可见像素数据。 合并单元随后将所选择的像素数据写入用于合成的帧缓冲器。
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6.发明授权Image processing apparatus having improved frame buffer with Z buffer and SAM port 失效具有Z缓冲器和SAM端口的具有改进的帧缓冲器的图像处理装置
公开(公告)号：US5621866A
公开(公告)日：1997-04-15
申请号：US94880
申请日：1993-07-22
申请人： Masahiro Murata , Takahiro Sakuraba
发明人： Masahiro Murata , Takahiro Sakuraba
CPC分类号： G09G5/393 , G06T15/405 , G09G5/395
摘要： An image processing apparatus for use in three-dimensional graphics has a frame buffer in a single device with a SAM port for simultaneously storing image information and depth information per pixel. For high speed pattern filling, the frame buffer has an image buffer for storing image information of a predetermined number of horizontal pixels in response to individual write permit signals for each pixel and a Z buffer for simultaneously outputting stored depth information and storing new depth information in response to write permit signals. A circuit identifying whether an image to be plotted is a horizontal line causes the predetermined number of pixels write permit signal output circuits to simultaneously calculate new depth information, compare the depth information read from the Z buffer with the calculated depth information and simultaneously output the write permit signals relative to the image buffer and Z buffer based on the comparison.
摘要翻译： 用于三维图形的图像处理装置具有在具有SAM端口的单个装置中的帧缓冲器，用于同时存储每像素的图像信息和深度信息。 对于高速图案填充，帧缓冲器具有用于响应于每个像素的各个写入允许信号而存储预定数量的水平像素的图像信息的图像缓冲器和用于同时输出存储的深度信息并将新的深度信息存储在其中的Z缓冲器 响应写许可信号。 识别要绘制的图像是否为水平线的电路使预定数量的像素写入允许信号输出电路同时计算新的深度信息，将从Z缓冲器读取的深度信息与计算出的深度信息进行比较，并同时输出写入 基于比较，允许相对于图像缓冲器和Z缓冲器的信号。
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公开(公告)号：US5572636A
公开(公告)日：1996-11-05
申请号：US460804
申请日：1995-06-02
CPC分类号： G06T15/04
摘要： A mode such that the same texture pattern is stored into a plurality of memories and is processed in parallel by a plurality of drawing processing units and a mode such that different texture patterns are stored into a plurality of memories and either one of the patterns is selected and processed in a time-division manner by a plurality of drawing processing units can be switched. When a pattern is enlarged and drawn at a rate of (1:N), variation values are added and the read-out coordinate values of the texture patterns are distributed, thereby making a block-like boundary inconspicuous. In the case where an underflow or overflow occurs in an adder to interpolate color values of the pixels, the well-known color value of the final pixel position is fixedly generated. In the case where the depth coordinate values of the whole picture plane which are drawn into frame buffers are equal, a single z value is written into a Z register without using a Z buffer. A special high-speed bus is provided as a local bus between a 3-dimensional drawing mechanism and a main memory control unit, thereby enabling the Z buffer area in a main storage unit to be directly accessed.
摘要翻译： 将相同的纹理图案存储到多个存储器中并由多个绘图处理单元并行处理的模式和使得不同的纹理图案被存储到多个存储器中并且选择任一个图案的模式 并且可以通过多个绘图处理单元以时分方式进行处理。 当以（1：N）的速率放大和绘制图案时，增加变化值，并且分布纹理图案的读出坐标值，从而使块状边界不显眼。 在加法器中发生下溢或溢出以内插像素的颜色值的情况下，固定地生成最终像素位置的公知颜色值。 在绘制到帧缓冲器中的整个画面的深度坐标值相等的情况下，将单个z值写入Z寄存器，而不使用Z缓冲器。 作为三维绘图机构和主存储器控制单元之间的局部总线提供特殊的高速总线，从而使得主存储单元中的Z缓冲区域能够被直接访问。
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