公开(公告)号：US20220404967A1

公开(公告)日：2022-12-22

申请号：US17701000

申请日：2022-03-22

Applicant: Hitachi, Ltd.

Inventor： Norio CHUJO

IPC: G06F3/06

Abstract: A storage system includes a CPU, a first memory module, a second memory module, and a storage device. The processor and the first memory module are installed in the same node. The second memory module are replaceable without shutting down power supply of the node. The first memory module stores an operating system and a program for managing user data to be stored in the storage device. The second memory module stores cache data of the user data to be stored in the storage device. The processor is configured to store a copy of data to be stored in the second memory module in the third memory module.

公开(公告)号：US20240431063A1

公开(公告)日：2024-12-26

申请号：US18595202

申请日：2024-03-04

Applicant: Hitachi, Ltd.

Inventor： Masahiro YAO ,  Norio CHUJO ,  Yutaka UEMATSU ,  Masahiro TOYAMA

IPC: H05K7/14 ,  G06F1/18 ,  H05K7/18

Abstract: The storage apparatus includes a midplane provided vertically to an installation surface of the storage apparatus and provided with a plurality of connectors arranged in parallel in an X-axis direction parallel to the installation surface of the storage apparatus; and a plurality of adapters on each of which two drive apparatuses are mounted and which are arranged in parallel in the X-axis direction and connected to the midplane through the plurality of respective connectors in a Y-axis direction parallel to the installation surface and vertical to the X-axis direction. Each of the adapters includes a board including a plurality of connectors connected to respective connectors of the two drive apparatuses which are arranged in parallel in the Y-axis direction, in the Y-axis direction, and a frame for mounting the two drive apparatuses arranged in parallel in the Y-axis direction and the board to each of the adapters.

公开(公告)号：US20240103740A1

公开(公告)日：2024-03-28

申请号：US18119255

申请日：2023-03-08

Applicant: Hitachi, Ltd.

Inventor： Norio CHUJO ,  Kentaro SHIMADA

IPC: G06F3/06 ,  G06F12/0804

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/067 ,  G06F12/0804

Abstract: A storage system having a plurality of control units that perform read control of data stored in a storage and write control of the data, the storage system comprising, each of the plurality of control units has a processor, a first memory connected to the processor and storing software for executing a process of read control and write control, a network interface for connecting to a control unit network that connects each of the plurality of control units, and a second memory connected to the network interface and storing control information of the data subject to read control and write control and cache data of the storage.

公开(公告)号：US20220013937A1

公开(公告)日：2022-01-13

申请号：US17328551

申请日：2021-05-24

Applicant: Hitachi, Ltd.

Inventor： Norio CHUJO ,  Yasuhiro IKEDA

IPC: H01R12/59 ,  H05K1/14 ,  H05K1/02 ,  H01R12/65 ,  H05K3/32

Abstract: A wiring substrate is connected to a backplane, and includes: a first connector that is mounted on one surface of the wiring substrate and is connected to the backplane; an opening portion that is formed in the one surface on a side opposite to a side connected to the backplane of the first connector, and through which a cable having one end connected to the first connector is passed; an integrated circuit that is mounted on the one surface on a side opposite to a side on which the first connector is present relative to the opening portion; and a second connector that is mounted on the other surface on a side opposite to the one surface in the vicinity of the integrated circuit on the side opposite to the side on which the first connector is present relative to the opening portion, is connected to the integrated circuit via a through hole penetrating the wiring substrate, and is connected to the other end of the cable.

公开(公告)号：US20240427713A1

公开(公告)日：2024-12-26

申请号：US18599738

申请日：2024-03-08

Applicant: Hitachi, Ltd.

Inventor： Norio CHUJO ,  Masanori TAKADA

IPC: G06F13/16 ,  G06F12/0868

Abstract: A storage apparatus includes a first controller having a first memory, a second controller having a second memory, and a memory module having a third memory. The first memory stores drive control information including a correspondence between a logical address and a physical address, first cache data in a data input-output (I/O) process, and first cache control information including a correspondence between a logical address and a cache address of the first cache data. The second memory stores drive control information, second cache data in the data I/O process, and second cache control information including a correspondence between a logical address and a cache address of the second cache data. The third memory stores first cache data provided with redundancy and second cache data provided with redundancy.

公开(公告)号：US20200260570A1

公开(公告)日：2020-08-13

申请号：US16758463

申请日：2017-12-13

Applicant: Hitachi, Ltd.

Inventor： Norio CHUJO ,  Yutaka UEMATSU ,  Masayoshi YAGYU

IPC: H05K1/02 ,  H05K1/11

Abstract: In a multilayer wiring board having through holes used in an electronic device, wiring is efficiently performed at high density while preventing crosstalk of differential signals. A wiring board includes: a plurality of pads arranged linearly at a predetermined pitch; a plurality of through holes arranged in parallel along an arrangement direction of the pads; and a wiring pattern connecting the pad to the through hole. Between the through holes connected to the pads which are connected to the ground via the wiring patterns, two through holes through which each of a pair of differential signals constituting a differential signal pair passes are provided such that a direction of a straight line connecting the two through holes is inclined to the arrangement direction of the pads.