公开(公告)号：US20240134806A1

公开(公告)日：2024-04-25

申请号：US18120827

申请日：2023-03-12

Applicant: Hitachi, Ltd.

Inventor： Kentaro SHIMADA ,  Masanori TAKADA

IPC: G06F12/1081 ,  G06F13/24

CPC classification number: G06F12/1081 ,  G06F13/24

Abstract: A protocol chip transmits the request from the host apparatus to a first processor through a first address translation unit. A first processor transmits a response to the request from the host apparatus, to the protocol chip through the first address translation unit. When the first processor stops processing, an instruction to transmit the request from the host apparatus to a second processor is transmitted to the protocol chip. When receiving the instruction to transmit the request from the host apparatus to the second processor, the protocol chip transmits the request from the host apparatus to the second processor through a second address translation unit. The second processor transmits the response to the request from the host apparatus to the protocol chip through the second address translation unit.

公开(公告)号：US20240103740A1

公开(公告)日：2024-03-28

申请号：US18119255

申请日：2023-03-08

Applicant: Hitachi, Ltd.

Inventor： Norio CHUJO ,  Kentaro SHIMADA

IPC: G06F3/06 ,  G06F12/0804

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/067 ,  G06F12/0804

Abstract: A storage system having a plurality of control units that perform read control of data stored in a storage and write control of the data, the storage system comprising, each of the plurality of control units has a processor, a first memory connected to the processor and storing software for executing a process of read control and write control, a network interface for connecting to a control unit network that connects each of the plurality of control units, and a second memory connected to the network interface and storing control information of the data subject to read control and write control and cache data of the storage.

公开(公告)号：US20230075635A1

公开(公告)日：2023-03-09

申请号：US17690965

申请日：2022-03-09

Applicant: Hitachi, Ltd.

Inventor： Kentaro SHIMADA ,  Takashi NAGAO ,  Naoya OKADA

IPC: G06F3/06

Abstract: A bandwidth between a second processor and a second memory is higher than a bandwidth between a first processor and a first memory. The first memory stores a read command from a host computer. The first processor analyzes a content of the read command, and in accordance with a result of the analysis, requests read data from the second processor. In response to the request from the first processor, the second processor reads the read data from one or more storage drives and stores the read data in the second memory. The second processor notifies the first processor that the read data is stored in the second memory. The first processor transfers the read data read from the second memory, to the host computer without storing the read data in the first memory.

公开(公告)号：US20240232099A9

公开(公告)日：2024-07-11

申请号：US18120827

申请日：2023-03-13

Applicant: Hitachi, Ltd.

Inventor： Kentaro SHIMADA ,  Masanori TAKADA

IPC: G06F12/1081 ,  G06F13/24

CPC classification number: G06F12/1081 ,  G06F13/24

Abstract: A protocol chip transmits the request from the host apparatus to a first processor through a first address translation unit. A first processor transmits a response to the request from the host apparatus, to the protocol chip through the first address translation unit. When the first processor stops processing, an instruction to transmit the request from the host apparatus to a second processor is transmitted to the protocol chip. When receiving the instruction to transmit the request from the host apparatus to the second processor, the protocol chip transmits the request from the host apparatus to the second processor through a second address translation unit. The second processor transmits the response to the request from the host apparatus to the protocol chip through the second address translation unit.

公开(公告)号：US20240069761A1

公开(公告)日：2024-02-29

申请号：US18179563

申请日：2023-03-07

Applicant: Hitachi, Ltd.

Inventor： Naoya OKADA ,  Kentaro SHIMADA ,  Yuki KOTAKE ,  Yukiyoshi TAKAMURA

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0655 ,  G06F3/0679

Abstract: A storage system includes a storage controller and a plurality of storage drives. The storage controller holds power management information for managing power supplied to the storage system and power consumption of an operating mounted device of the storage system, and definition information for defining a relationship between power states and power consumption of the plurality of storage drives. The storage controller determines a power budget that can be supplied to the plurality of storage drives, based on the power management information according to a change in a configuration of the storage system, and determines a power state of each of the plurality of storage drives based on the power budget and the definition information.

公开(公告)号：US20230205419A1

公开(公告)日：2023-06-29

申请号：US18118249

申请日：2023-03-07

Applicant: Hitachi, Ltd.

Inventor： Masahiro TSURUYA ,  Nagamasa MIZUSHIMA ,  Tomohiro YOSHIHARA ,  Kentaro SHIMADA

IPC: G06F3/06 ,  G06F16/174

CPC classification number: G06F3/0608 ,  G06F3/0641 ,  G06F16/1744 ,  G06F3/0659 ,  H03M7/70

Abstract: The storage device includes a first memory, a process device that stores data in the first memory and reads the data from the first memory, and an accelerator that includes a second memory different from the first memory. The accelerator stores compressed data stored in one or more storage drives storing data, in the second memory, decompresses the compressed data stored in the second memory to generate plaintext data, extracts data designated in the process device from the plaintext data, and transmits the extracted designated data to the first memory.

公开(公告)号：US20230136735A1

公开(公告)日：2023-05-04

申请号：US18083653

申请日：2022-12-19

Applicant: Hitachi, Ltd.

Inventor： Naoya OKADA ,  Takashi NAGAO ,  Kentaro SHIMADA ,  Ryosuke TATSUMI ,  Sadahiro SUGIMOTO

IPC: G06F3/06

Abstract: The present disclosure is to optimize processes in a storage system. A storage system includes: a first controller including a first computing device and a first memory; a second controller including a second computing device and a second memory; and an interface circuit that transfers data between the first controller and the second controller. The interface circuit reads first compressed data from the second memory. The interface circuit decompresses the first compressed data to generate first uncompressed data, and writes the first uncompressed data into the first memory.

公开(公告)号：US20220164146A1

公开(公告)日：2022-05-26

申请号：US17472845

申请日：2021-09-13

Applicant: Hitachi, Ltd.

Inventor： Masahiro TSURUYA ,  Norio SHIMOZONO ,  Akira YAMAMOTO ,  Kentaro SHIMADA ,  Takashi NAGAO

IPC: G06F3/06

Abstract: A storage system includes: a controller which includes a processor and a memory; and one or more storage devices. The controller sets a plurality of logical volumes, stores data related to a write request in the memory when the write request is received in the logical volume, and collectively compresses a plurality of pieces of data related to the write request in the memory and writes the compressed data to the storage device. When a plurality of pieces of data related to a plurality of the logical volumes that need to be written to the storage device exist in the memory, the controller selects the plurality of pieces of data in an identical logical volume, and collectively compresses the plurality of pieces of selected data and writes the compressed data in the storage device.

公开(公告)号：US20250077098A1

公开(公告)日：2025-03-06

申请号：US18591082

申请日：2024-02-29

Applicant: Hitachi, Ltd.

Inventor： Kentaro SHIMADA

IPC: G06F3/06

Abstract: Provided herein is a storage system capable of reducing power consumption. Each of a plurality of controllers provided to a storage system includes a plurality of first power feeding areas of which electric power is independently controllable, and a processor which processes an input/output request and a memory connected to the processor. The processor and the memory are provided to each first power feeding area. Each of the plurality of controllers is configured as being switchable between a first operating mode in which all the first power feeding areas provided to the controller are made in a working state, and a second operating mode in which one or some of the first power feeding areas provided to the controller are made in a stopped state, and the rest of the first power feeding areas is made in the working state.

公开(公告)号：US20240319923A1

公开(公告)日：2024-09-26

申请号：US18735412

申请日：2024-06-06

Applicant: Hitachi, Ltd.

Inventor： Nagamasa MIZUSHIMA ,  Kentaro SHIMADA

IPC: G06F3/06 ,  G06F7/523 ,  H03M7/30

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F7/523 ,  H03M7/3084 ,  H03M7/6005

Abstract: To speed up decoding of a range code. A decompression circuit calculates a plurality of candidate bit values for each bit of the N-bit string based on a plurality of possible bit histories of a bit before a K-th bit in parallel for a plurality of bits, and repeatedly selects a correct bit value of the K-th bit from the plurality of candidate bit values based on a correct bit history of the bit before the K-th bit to decode the N-bit string.