-
1.
公开(公告)号:US20240372469A1
公开(公告)日:2024-11-07
申请号:US18285796
申请日:2022-02-16
Applicant: Hitachi Astemo, Ltd.
Inventor: Masato KITA , Yoichiro KOBAYASHI
Abstract: Provided are a highly reliable load drive circuit that includes a switching circuit that selects a power supply voltage, and is capable of seamlessly switching the power supply voltage without using a switch or a determination circuit, an electronic control device using the load drive circuit, and a control method for the electronic control device. The load drive circuit includes: a booster circuit that boosts an output from a power supply; and a voltage switching circuit that switches the output from the power supply and an output from the booster circuit, in which the voltage switching circuit includes a first MOSFET, a second MOSFET, and a gate voltage generation circuit that generates gate voltages of the first MOSFET and the second MOSFET, gate terminals of the first MOSFET and the second MOSFET are connected to the gate voltage generation circuit, source terminals of the first MOSFET and the second MOSFET are connected to the same node, a drain terminal of the first MOSFET is connected to an output terminal of the booster circuit, a drain terminal of the second MOSFET is connected to an output terminal of the power supply, and the output from the power supply and the output from the booster circuit are seamlessly switched according to an output voltage from the power supply.
-
公开(公告)号:US20220020702A1
公开(公告)日:2022-01-20
申请号:US17293617
申请日:2019-11-27
Applicant: Hitachi Astemo, Ltd.
Inventor: Katsumi IKEGAYA , Takayuki OSHIMA , Yoichiro KOBAYASHI , Masato KITA , Keishi KOMORIYAMA , Minoru MIGITA , Yu KAWAGOE , Kiyotaka KANNO
IPC: H01L23/00 , H01L27/088 , H01L23/522 , H01L23/528 , B60R16/03
Abstract: In a semiconductor device equipped with a current mirror circuit, a highly reliable semiconductor device capable of suppressing a change in a mirror ratio of the current mirror circuit over time is provided. A current mirror circuit that includes a first MOS transistor and a plurality of MOS transistors paired with the first MOS transistor, and a plurality of wiring layers formed on an upper layer of the MOS transistor are provided. The plurality of wiring layers are arranged such that wiring patterns have the same shape within a predetermined range from an end of a channel region of each of the first MOS transistor and the plurality of MOS transistors.
-