公开(公告)号：US20220221891A1

公开(公告)日：2022-07-14

申请号：US17611646

申请日：2020-05-15

Applicant: Hitachi Astemo, Ltd.

Inventor： Katsumi IKEGAYA ,  Yoichiro KOBAYASHI ,  Minoru MIGITA

IPC: G05F3/26 ,  H01L21/8234

Abstract: In a semiconductor device including a current mirror circuit, a highly reliable semiconductor device that reduces a variation in a mirror ratio of the current mirror circuit and suppresses a change with time in a pairing property of elements can be provided.

公开(公告)号：US20240186046A1

公开(公告)日：2024-06-06

申请号：US18279421

申请日：2021-09-10

Applicant: Hitachi Astemo, Ltd.

Inventor： Keishi KOMORIYAMA ,  Yoichiro KOBAYASHI ,  Minoru MIGITA

IPC: H01F7/06 ,  F16H61/12 ,  H02M3/16

CPC classification number: H01F7/064 ,  F16H61/12 ,  H02M3/16 ,  F16H2061/1232 ,  F16H2061/1292

Abstract: There is provided a power saving and highly reliable semiconductor device on which a switching power supply circuit and a driver circuit are mounted together, and which can perform appropriate control by the driver circuit even when a battery terminal is disconnected while reducing power loss in the entire semiconductor device. The semiconductor device includes: a first terminal which is connected to a battery power source; a switching power supply circuit which steps down a battery voltage input from the first terminal; a second terminal which is connected to a switching power source different from the battery power source; a regulator circuit which steps down a voltage input from the second terminal; and a predriver circuit which is connected to the regulator circuit.

公开(公告)号：US20220020702A1

公开(公告)日：2022-01-20

申请号：US17293617

申请日：2019-11-27

Applicant: Hitachi Astemo, Ltd.

Inventor： Katsumi IKEGAYA ,  Takayuki OSHIMA ,  Yoichiro KOBAYASHI ,  Masato KITA ,  Keishi KOMORIYAMA ,  Minoru MIGITA ,  Yu KAWAGOE ,  Kiyotaka KANNO

IPC: H01L23/00 ,  H01L27/088 ,  H01L23/522 ,  H01L23/528 ,  B60R16/03

Abstract: In a semiconductor device equipped with a current mirror circuit, a highly reliable semiconductor device capable of suppressing a change in a mirror ratio of the current mirror circuit over time is provided. A current mirror circuit that includes a first MOS transistor and a plurality of MOS transistors paired with the first MOS transistor, and a plurality of wiring layers formed on an upper layer of the MOS transistor are provided. The plurality of wiring layers are arranged such that wiring patterns have the same shape within a predetermined range from an end of a channel region of each of the first MOS transistor and the plurality of MOS transistors.