公开(公告)号：US07372744B2

公开(公告)日：2008-05-13

申请号：US11216215

申请日：2005-09-01

申请人： Hitoshi Shiga ,  Chih-Chung Chen ,  Chih-Hung Wang ,  Sheng-Lin Hung

发明人： Hitoshi Shiga ,  Chih-Chung Chen ,  Chih-Hung Wang ,  Sheng-Lin Hung

IPC分类号： G11C7/10

CPC分类号： G11C16/102 ,  G11C16/0483 ,  G11C16/26 ,  G11C2207/2236 ,  G11C2216/14

摘要： A memory system includes a memory cell array, a bit line switch, first and second page buffers, a column switch, an error correction circuit, and control circuits. The second page buffer can swap data with the first page buffer. The control circuits controls the bit line switch and the first and second page buffers, sequentially reads, page by page, one or more pages from the mth (m is a positive integer) page to the nth (n is an integer greater than m) page of the first block in the memory cell array, controls the error correction circuit to perform error correction calculation by the error correction circuit, controls the first and second data buffers and the bit line switch, and controls to perform write in the second block in the erase state in the memory cell array.

摘要翻译： 存储器系统包括存储单元阵列，位线开关，第一和第二页缓冲器，列开关，纠错电路和控制电路。 第二页缓冲区可以与第一页缓冲区交换数据。 控制电路控制位线开关，第一和第二页缓冲器逐页依次读取从第m（m为正整数）页到第n（n为大于m的整数）的一页或多页， 控制误差校正电路进行误差校正电路的误差校正计算，控制第一和第二数据缓冲器和位线开关，并控制在第二块中执行写入 存储单元阵列中的擦除状态。

公开(公告)号：US20060050314A1

公开(公告)日：2006-03-09

申请号：US11216215

申请日：2005-09-01

申请人： Hitoshi Shiga ,  Chih-Chung Chen ,  Chih-Hung Wang ,  Sheng-Lin Hung

发明人： Hitoshi Shiga ,  Chih-Chung Chen ,  Chih-Hung Wang ,  Sheng-Lin Hung

IPC分类号： G06K15/00

CPC分类号： G11C16/102 ,  G11C16/0483 ,  G11C16/26 ,  G11C2207/2236 ,  G11C2216/14

摘要： A memory system includes a memory cell array, a bit line switch, first and second page buffers, a column switch, an error correction circuit, and control circuits. The second page buffer can swap data with the first page buffer. The control circuits controls the bit line switch and the first and second page buffers, sequentially reads, page by page, one or more pages from the mth (m is a positive integer) page to the nth (n is an integer greater than m) page of the first block in the memory cell array, controls the error correction circuit to perform error correction calculation by the error correction circuit, controls the first and second data buffers and the bit line switch, and controls to perform write in the second block in the erase state in the memory cell array.

摘要翻译： 存储器系统包括存储单元阵列，位线开关，第一和第二页缓冲器，列开关，纠错电路和控制电路。 第二页缓冲区可以与第一页缓冲区交换数据。 控制电路控制位线开关，第一和第二页缓冲器逐页依次读取从第m（m为正整数）页到第n（n为大于m的整数）的一页或多页， 控制误差校正电路进行误差校正电路的误差校正计算，控制第一和第二数据缓冲器和位线开关，并控制在第二块中执行写入 存储单元阵列中的擦除状态。