公开(公告)号：US20080191765A1

公开(公告)日：2008-08-14

申请号：US12028936

申请日：2008-02-11

申请人： Ho-young KIM ,  Dong-bee JANG ,  Jae-yoon SIM ,  Young-sang KIM

发明人： Ho-young KIM ,  Dong-bee JANG ,  Jae-yoon SIM ,  Young-sang KIM

IPC分类号： H03L7/00 ,  G11C5/14 ,  G05F3/16

CPC分类号： H03L7/0812 ,  H03L7/10

摘要： A broadband multi-phase output delay locked loop (DLL) circuit can be operated in a wide range of frequencies and generate various phases. Unlike conventional voltage control delay lines in which delay cells are connected in series, the DLL circuit utilizes a delay matrix in which a resistant network is used so that the number of delay cells connected in series is reduced, various phases can be outputted, and a delay interval error (phase error) due to the resistant network is minimized. The current of the delay cells is controlled so that the delay cells in the delay matrix can operate in a wide range of frequencies, and load capacitance values of capacitors connected in parallel in the delay cells can be controlled.

摘要翻译： 宽带多相输出延迟锁定环（DLL）电路可以在宽频率范围内工作，并产生各种相位。 与其中延迟单元串联连接的常规电压控制延迟线不同，DLL电路利用其中使用电阻网络的延迟矩阵，使得串联连接的延迟单元的数量减少，可以输出各种相位，并且 由于抵抗网络导致的延迟间隔误差（相位误差）被最小化。 控制延迟单元的电流，使得延迟矩阵中的延迟单元可以在宽的频率范围内工作，并且可以控制在延迟单元中并联连接的电容器的负载电容值。