公开(公告)号：US09363119B1

公开(公告)日：2016-06-07

申请号：US14812827

申请日：2015-07-29

Applicant: Honeywell International Inc.

Inventor： Balakrishna G. Gudi ,  Dinesh Kumar Kn ,  Aravind Sathyanarayana ,  Sandeep Pai

IPC: H04L27/14 ,  H04B1/10

CPC classification number: H04L27/14 ,  H04L27/1563

Abstract: A method of FSK decoding includes generating a pulse waveform (R'Edge) from a received FSK encoded signal (FSK signal) and a system clock (Sys_clk). From R'Edge and Sys_clk clocks are generated including a first clock and second clock framing a logic ‘0’ level of the FSK signal, and a third clock and fourth clock framing a logic ‘1’ level of the FSK signal. At least four frequency envelopes are generated from the clocks including a logic ‘0’ envelope, a logic ‘1’ envelope, a lower frequency envelope below the logic ‘0’ envelope, and an upper frequency envelope above the logic ‘1’ envelope. R'Edge is compared to the four envelopes, and a decoded output is produced, logic ‘0’ if the R'Edge overlaps the logic ‘0’ envelope, logic ‘1’ if R'Edge overlaps the logic ‘1’ envelope, and a previous output state if R'Edge does not overlap the logic ‘0’ or logic ‘1’ envelope.

Abstract translation: FSK解码的方法包括从接收的FSK编码信号（FSK信号）和系统时钟（Sys_clk）产生脉冲波形（R'Edge）。 从R'Edge和Sys_clk时钟产生，包括构成FSK信号的逻辑“0”电平的第一时钟和第二时钟，以及构成FSK信号的逻辑“1”电平的第三时钟和第四时钟。 从包括逻辑'0'包络，逻辑'1'包络，低于逻辑“0”包络的较低频率包络以及逻辑“1”包络以上的较高频率包络的时钟产生至少四个频率包络。 将R'Edge与四个信封进行比较，并产生解码输出，如果R'Edge与逻辑“0”包络重叠，逻辑“0”，如果R'Edge与逻辑'1'信封重叠，逻辑'1' 如果R'Edge不与逻辑“0”或逻辑“1”包络重叠，则为先前的输出状态。