公开(公告)号：US20140132306A1

公开(公告)日：2014-05-15

申请号：US13675828

申请日：2012-11-13

申请人： HONEYWELL INTERNATIONAL INC.

发明人： Paul S. Fechner ,  Weston Roper ,  James D. Seefeldt

IPC分类号： H03K19/094

CPC分类号： H03K19/09421 ,  H03K3/01

摘要： This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.

摘要翻译： 本公开涉及用于在CMOS逻辑电路中实现内部主体偏置电路的装置，集成电路，系统和方法。 在一个示例中，CMOS逻辑电路形成在集成电路中。 CMOS逻辑电路包括PMOS晶体管，NMOS晶体管; 以及在集成电路中形成的主体偏置电路。 体引线偏置电路耦合在PMOS晶体管的主体连接端子和NMOS晶体管的主体连接端子之间。

公开(公告)号：US10139849B2

公开(公告)日：2018-11-27

申请号：US15497051

申请日：2017-04-25

申请人： Honeywell International Inc.

发明人： Xiaoxin Feng ,  Weston Roper

IPC分类号： H03F3/00 ,  G05F3/26 ,  G05F3/16 ,  G05F1/10 ,  G05F3/30 ,  G05F3/24 ,  H03K17/082 ,  H03K19/003 ,  H03K5/00

摘要： The disclosure is directed to a simple, inexpensive circuit to extract the complementary metal-oxide-semiconductor (CMOS) threshold voltage (Vt) from an integrated circuit. The threshold voltage may be used elsewhere in the circuit for a variety of purposes. One example use of threshold voltage is to sense the temperature of the circuit. The CMOS Vt extraction circuit of this disclosure includes a current mirror and an arrangement of well-matched transistors and resistors that takes advantage of the square law equation. The structure of the circuit may make it well suited to applications that benefit from low-power radiation hardened circuits.

公开(公告)号：US20180307262A1

公开(公告)日：2018-10-25

申请号：US15497051

申请日：2017-04-25

申请人： Honeywell International Inc.

发明人： Xiaoxin Feng ,  Weston Roper

IPC分类号： G05F3/24 ,  H03K17/082 ,  H03K19/003 ,  G05F3/26 ,  G05F1/10

CPC分类号： G05F3/242 ,  G05F1/10 ,  G05F3/26 ,  H03K17/0822 ,  H03K19/00384 ,  H03K2005/0028

摘要： The disclosure is directed to a simple, inexpensive circuit to extract the complementary metal-oxide-semiconductor (CMOS) threshold voltage (Vt) from an integrated circuit. The threshold voltage may be used elsewhere in the circuit for a variety of purposes. One example use of threshold voltage is to sense the temperature of the circuit. The CMOS Vt extraction circuit of this disclosure includes a current mirror and an arrangement of well-matched transistors and resistors that takes advantage of the square law equation. The structure of the circuit may make it well suited to applications that benefit from low-power radiation hardened circuits.

公开(公告)号：US08975952B2

公开(公告)日：2015-03-10

申请号：US13675828

申请日：2012-11-13

申请人： Honeywell International Inc.

发明人： Paul S. Fechner ,  Weston Roper ,  James D. Seefeldt

IPC分类号： H03K3/01 ,  H03K19/094

CPC分类号： H03K19/09421 ,  H03K3/01

摘要： This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.

摘要翻译： 本公开涉及用于在CMOS逻辑电路中实现内部主体偏置电路的装置，集成电路，系统和方法。 在一个示例中，CMOS逻辑电路形成在集成电路中。 CMOS逻辑电路包括PMOS晶体管，NMOS晶体管; 以及在集成电路中形成的主体偏置电路。 体引线偏置电路耦合在PMOS晶体管的主体连接端子和NMOS晶体管的主体连接端子之间。