公开(公告)号：US07606336B2

公开(公告)日：2009-10-20

申请号：US11342566

申请日：2006-01-31

申请人： Jeong-won Lee ,  Hyong-suk Kim ,  Hong-rak Son ,  Hyun-jung Kim

发明人： Jeong-won Lee ,  Hyong-suk Kim ,  Hong-rak Son ,  Hyun-jung Kim

IPC分类号： H04L27/06

CPC分类号： H03M13/6343 ,  H03M13/41 ,  H03M13/6597

摘要： An analog Viterbi decoder for decoding an analog signal is provided that includes a plurality of decoding units, provided with a plurality of processing parts each having a plurality of cells arranged to correspond to respective nodes of a trellis diagram, for decoding analog input data using an analog signal processing cell having a circulation type connection structure in which the last processing part is connected to the first processing part; a control unit for performing in parallel a sequential designation of the processing parts with respect to the decoding units; an analog data storage unit including a plurality of capacitors connected in parallel with the processing parts provided in the decoding units; and a first switch unit for storing analog input data in a specific capacitor of the analog data storage units under the control of the control unit. Accordingly, the decoding speed can be remarkably improved.

摘要翻译： 提供了一种用于解码模拟信号的模拟维特比解码器，其包括多个解码单元，其具有多个处理部件，每个处理部件具有布置成对应于格状图的各个节点的多个单元，用于使用 具有循环型连接结构的模拟信号处理单元，其中最后一个处理部分连接到第一处理部分; 控制单元，用于并行地执行关于解码单元的处理部分的顺序指定; 模拟数据存储单元，包括与设置在解码单元中的处理部并联连接的多个电容器; 以及第一开关单元，用于在控制单元的控制下将模拟输入数据存储在模拟数据存储单元的特定电容器中。 因此，可以显着提高解码速度。

公开(公告)号：US20070047677A1

公开(公告)日：2007-03-01

申请号：US11487469

申请日：2006-07-17

申请人： Hong-rak Son ,  Hyun-jung Kim ,  Hyong-suk Kim ,  Jeong-won Lee

发明人： Hong-rak Son ,  Hyun-jung Kim ,  Hyong-suk Kim ,  Jeong-won Lee

IPC分类号： H03D1/00

CPC分类号： H03M13/413 ,  H03M13/6597

摘要： A circular Viterbi decoder is capable of improving a data decoding speed without being limited by a sampling speed of a sampling and holding circuit. An analog Viterbi decoder includes: a clock divider which generates a plurality of clock signals by dividing a clock frequency of an externally-input clock signal, a plurality of sampling and holding units which sample and hold input analog data according to the clock signals generated from the clock divider, and a multiplexer which sequentially and alternately outputs the analog data sampled and held by the sampling and holding units.

摘要翻译： 圆形维特比解码器能够提高数据解码速度，而不受采样和保持电路的采样速度的限制。 模拟维特比解码器包括：时钟分频器，其通过除外部输入的时钟信号的时钟频率产生多个时钟信号;多个采样和保持单元，其根据从...生成的时钟信号采样和保持输入模拟数据; 时钟分频器和多路复用器，其顺序并交替地输出由采样和保持单元采样和保持的模拟数据。

公开(公告)号：US07751507B2

公开(公告)日：2010-07-06

申请号：US11487469

申请日：2006-07-17

申请人： Hong-rak Son ,  Hyun-jung Kim ,  Hyong-suk Kim ,  Jeong-won Lee

发明人： Hong-rak Son ,  Hyun-jung Kim ,  Hyong-suk Kim ,  Jeong-won Lee

IPC分类号： H03D1/00

CPC分类号： H03M13/413 ,  H03M13/6597

摘要： A circular Viterbi decoder is capable of improving a data decoding speed without being limited by a sampling speed of a sampling and holding circuit. An analog Viterbi decoder includes: a clock divider which generates a plurality of clock signals by dividing a clock frequency of an externally-input clock signal, a plurality of sampling and holding units which sample and hold input analog data according to the clock signals generated from the clock divider, and a multiplexer which sequentially and alternately outputs the analog data sampled and held by the sampling and holding units.

摘要翻译： 圆形维特比解码器能够提高数据解码速度，而不受采样和保持电路的采样速度的限制。 模拟维特比解码器包括：时钟分频器，其通过除外部输入的时钟信号的时钟频率产生多个时钟信号;多个采样和保持单元，其根据从...生成的时钟信号采样和保持输入模拟数据; 时钟分频器和多路复用器，其顺序并交替地输出由采样和保持单元采样和保持的模拟数据。

公开(公告)号：US20060171490A1

公开(公告)日：2006-08-03

申请号：US11342566

申请日：2006-01-31

申请人： Jeong-won Lee ,  Hyong-suk Kim ,  Hong-rak Son ,  Hyun-jung Kim

发明人： Jeong-won Lee ,  Hyong-suk Kim ,  Hong-rak Son ,  Hyun-jung Kim

IPC分类号： H03D1/00 ,  H03M13/03

CPC分类号： H03M13/6343 ,  H03M13/41 ,  H03M13/6597

摘要： An analog Viterbi decoder for decoding an analog signal is provided that includes a plurality of decoding units, provided with a plurality of processing parts each having a plurality of cells arranged to correspond to respective nodes of a trellis diagram, for decoding analog input data using an analog signal processing cell having a circulation type connection structure in which the last processing part is connected to the first processing part; a control unit for performing in parallel a sequential designation of the processing parts with respect to the decoding units; an analog data storage unit including a plurality of capacitors connected in parallel with the processing parts provided in the decoding units; and a first switch unit for storing analog input data in a specific capacitor of the analog data storage units under the control of the control unit. Accordingly, the decoding speed can be remarkably improved.