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    DYNAMIC BUFFER MANAGEMENT IN HIGH-THROUGHPUT WIRELESS SYSTEMS
    3.
    发明申请
    DYNAMIC BUFFER MANAGEMENT IN HIGH-THROUGHPUT WIRELESS SYSTEMS 审中-公开
    高速无线系统中的动态缓存管理

    公开(公告)号：US20130215745A1

    公开(公告)日：2013-08-22

    申请号：US13398440

    申请日：2012-02-16

    申请人： Srikanth Shubhakoti ,  Hyun-Gyu Jeon ,  Hongyu Xie ,  Gang Lu

    发明人： Srikanth Shubhakoti ,  Hyun-Gyu Jeon ,  Hongyu Xie ,  Gang Lu

    IPC分类号： H04W28/14

    CPC分类号： H04L1/1867

    摘要： Dynamic buffer management for wireless communication systems facilitates enhanced throughput. The dynamic buffer management reduces buffer allocation for the current service period near the end of the current service period, and allocates the freed buffer space to one or more subsequent service periods before they begin. As a result, the host may begin to transfer data for those subsequent service periods in advance, so that data is immediately available to send when the subsequent service periods begin.

    摘要翻译： 无线通信系统的动态缓冲区管理有助于提高吞吐量。 动态缓冲区管理可以减少当前服务期限附近的当前服务期间的缓冲区分配，并将释放的缓冲区空间分配到其开始之前的一个或多个后续服务周期。 结果，主机可以提前开始传送那些后续服务周期的数据，这样当随后的服务周期开始时，数据立即可用于发送。

    MAC processor architecture
    4.
    发明授权
    MAC processor architecture 有权
    MAC处理器架构

    公开(公告)号：US08897293B1

    公开(公告)日：2014-11-25

    申请号：US13465907

    申请日：2012-05-07

    申请人： Bhaskar Chowdhuri ,  Srikanth Shubhakoti ,  Vinod Ananth ,  Hongyu Xie ,  Shui Cheong Lee

    发明人： Bhaskar Chowdhuri ,  Srikanth Shubhakoti ,  Vinod Ananth ,  Hongyu Xie ,  Shui Cheong Lee

    IPC分类号： H04Q11/00

    CPC分类号： G06F9/461

    摘要： In a media access control (MAC) processor, a programmable controller is configured to execute machine readable instructions for implementing MAC functions corresponding to data received by a communication device. A tightly coupled memory is associated with the programmable controller. A system memory is coupled to the programmable controller via a system bus, and a hardware processor is coupled to the system bus and the tightly coupled memory. The hardware processor is configured to implement MAC functions on data received in a communication frame, store, in the tightly coupled memory, processed data corresponding to data in the communication frame that indicates a structure of downlink data in the communication frame, and store, in the system memory, processed data corresponding to other data in the communication frame.

    摘要翻译： 在媒体访问控制（MAC）处理器中，可编程控制器被配置为执行用于实现与由通信设备接收的数据相对应的MAC功能的机器可读指令。 紧密耦合的存储器与可编程控制器相关联。 系统存储器经由系统总线耦合到可编程控制器，并且硬件处理器耦合到系统总线和紧耦合的存储器。 硬件处理器被配置为对通信帧中接收到的数据实现MAC功能，在紧耦合的存储器中存储对应于指示通信帧中的下行链路数据的结构的通信帧中的数据的处理数据，并存储在 系统存储器，对应于通信帧中的其他数据的处理数据。

    WiMAX MAC
    5.
    发明授权
    WiMAX MAC 有权

    公开(公告)号：US08175015B1

    公开(公告)日：2012-05-08

    申请号：US12334218

    申请日：2008-12-12

    申请人： Bhaskar Chowdhuri ,  Srikanth Shubhakoti ,  Vinod Ananth ,  Hongyu Xie ,  Shui Cheong Lee

    发明人： Bhaskar Chowdhuri ,  Srikanth Shubhakoti ,  Vinod Ananth ,  Hongyu Xie ,  Shui Cheong Lee

    IPC分类号： H04L5/22

    CPC分类号： G06F9/461

    摘要： A media access control (MAC) processor includes a programmable controller and a memory coupled to the programmable controller to store machine readable instructions for implementing MAC functions corresponding to data received by a communication device. A hardware processor is coupled to the programmable controller. The hardware processor includes a processing engine configured to implement MAC functions on the data received by the communication device. The hardware processor additionally includes a context memory coupled to the processing engine to store state information of the processing engine corresponding to one or more contexts, and context switch logic coupled to the processing to determine when the processing engine should switch contexts.

    摘要翻译： 媒体访问控制（MAC）处理器包括可编程控制器和耦合到可编程控制器的存储器，用于存储用于实现与由通信设备接收的数据相对应的MAC功能的机器可读指令。 硬件处理器耦合到可编程控制器。 硬件处理器包括被配置为对通信设备接收的数据实现MAC功能的处理引擎。 硬件处理器还包括耦合到处理引擎的上下文存储器，以存储对应于一个或多个上下文的处理引擎的状态信息，以及耦合到该处理的上下文切换逻辑，以确定处理引擎何时切换上下文。