公开(公告)号：US08897293B1

公开(公告)日：2014-11-25

申请号：US13465907

申请日：2012-05-07

申请人： Bhaskar Chowdhuri ,  Srikanth Shubhakoti ,  Vinod Ananth ,  Hongyu Xie ,  Shui Cheong Lee

发明人： Bhaskar Chowdhuri ,  Srikanth Shubhakoti ,  Vinod Ananth ,  Hongyu Xie ,  Shui Cheong Lee

IPC分类号： H04Q11/00

CPC分类号： G06F9/461

摘要： In a media access control (MAC) processor, a programmable controller is configured to execute machine readable instructions for implementing MAC functions corresponding to data received by a communication device. A tightly coupled memory is associated with the programmable controller. A system memory is coupled to the programmable controller via a system bus, and a hardware processor is coupled to the system bus and the tightly coupled memory. The hardware processor is configured to implement MAC functions on data received in a communication frame, store, in the tightly coupled memory, processed data corresponding to data in the communication frame that indicates a structure of downlink data in the communication frame, and store, in the system memory, processed data corresponding to other data in the communication frame.

摘要翻译： 在媒体访问控制（MAC）处理器中，可编程控制器被配置为执行用于实现与由通信设备接收的数据相对应的MAC功能的机器可读指令。 紧密耦合的存储器与可编程控制器相关联。 系统存储器经由系统总线耦合到可编程控制器，并且硬件处理器耦合到系统总线和紧耦合的存储器。 硬件处理器被配置为对通信帧中接收到的数据实现MAC功能，在紧耦合的存储器中存储对应于指示通信帧中的下行链路数据的结构的通信帧中的数据的处理数据，并存储在 系统存储器，对应于通信帧中的其他数据的处理数据。

公开(公告)号：US08175015B1

公开(公告)日：2012-05-08

申请号：US12334218

申请日：2008-12-12

申请人： Bhaskar Chowdhuri ,  Srikanth Shubhakoti ,  Vinod Ananth ,  Hongyu Xie ,  Shui Cheong Lee

发明人： Bhaskar Chowdhuri ,  Srikanth Shubhakoti ,  Vinod Ananth ,  Hongyu Xie ,  Shui Cheong Lee

IPC分类号： H04L5/22

CPC分类号： G06F9/461

摘要： A media access control (MAC) processor includes a programmable controller and a memory coupled to the programmable controller to store machine readable instructions for implementing MAC functions corresponding to data received by a communication device. A hardware processor is coupled to the programmable controller. The hardware processor includes a processing engine configured to implement MAC functions on the data received by the communication device. The hardware processor additionally includes a context memory coupled to the processing engine to store state information of the processing engine corresponding to one or more contexts, and context switch logic coupled to the processing to determine when the processing engine should switch contexts.

摘要翻译： 媒体访问控制（MAC）处理器包括可编程控制器和耦合到可编程控制器的存储器，用于存储用于实现与由通信设备接收的数据相对应的MAC功能的机器可读指令。 硬件处理器耦合到可编程控制器。 硬件处理器包括被配置为对通信设备接收的数据实现MAC功能的处理引擎。 硬件处理器还包括耦合到处理引擎的上下文存储器，以存储对应于一个或多个上下文的处理引擎的状态信息，以及耦合到该处理的上下文切换逻辑，以确定处理引擎何时切换上下文。

公开(公告)号：US08514882B1

公开(公告)日：2013-08-20

申请号：US13474999

申请日：2012-05-18

申请人： Bhaskar Chowdhuri ,  Shui Cheong Lee ,  Hongyu Xie ,  Yashodhara Devadiga ,  Raja Banerjea

发明人： Bhaskar Chowdhuri ,  Shui Cheong Lee ,  Hongyu Xie ,  Yashodhara Devadiga ,  Raja Banerjea

IPC分类号： H04W88/06

CPC分类号： H04J3/1694 ,  H04W74/04

摘要： Embodiments of the present invention provide a method that includes receiving, by a traffic arbiter, a predetermined time-slot allocation of one or more uplink time slots and/or one or more downlink time slots for a first wireless media access control (MAC) configured to operate within a first wireless transmission system. The method also includes determining, by the traffic arbiter, whether to grant a second wireless MAC, configured to operate within a second wireless transmission system, permission to transmit or receive based at least in part on the predetermined time-slot allocation.

摘要翻译： 本发明的实施例提供一种方法，其包括由业务仲裁器接收针对配置的第一无线媒体访问控制（MAC）的一个或多个上行链路时隙和/或一个或多个下行链路时隙的预定时隙分配 以在第一无线传输系统内操作。 该方法还包括由业务仲裁器确定是否授予被配置为在第二无线传输系统内操作的第二无线MAC，至少部分地基于预定时隙分配来发送或接收许可。

公开(公告)号：US08184658B1

公开(公告)日：2012-05-22

申请号：US12334319

申请日：2008-12-12

申请人： Bhaskar Chowdhuri ,  Shui Cheong Lee ,  Hongyu Xie ,  Yashodhara Devadiga ,  Raja Banerjea

发明人： Bhaskar Chowdhuri ,  Shui Cheong Lee ,  Hongyu Xie ,  Yashodhara Devadiga ,  Raja Banerjea

IPC分类号： H04W88/06

CPC分类号： H04J3/1694 ,  H04W74/04

摘要： Embodiments of the present invention provide a method that includes receiving, by a traffic arbiter, a predetermined time-slot allocation of one or more uplink time slots and/or one or more downlink time slots for a first wireless media access control (MAC) configured to operate within a first wireless transmission system. The method also includes determining, by the traffic arbiter, whether to grant a second wireless MAC, configured to operate within a second wireless transmission system, permission to transmit or receive based at least in part on the predetermined time-slot allocation.

摘要翻译： 本发明的实施例提供一种方法，其包括由业务仲裁器接收针对配置的第一无线媒体访问控制（MAC）的一个或多个上行链路时隙和/或一个或多个下行链路时隙的预定时隙分配 以在第一无线传输系统内操作。 该方法还包括由业务仲裁器确定是否授予被配置为在第二无线传输系统内操作的第二无线MAC，至少部分地基于预定时隙分配来发送或接收许可。

公开(公告)号：US06674443B1

公开(公告)日：2004-01-06

申请号：US09476486

申请日：1999-12-30

申请人： Bhaskar Chowdhuri ,  Kanwal Preet Singh Banga ,  Frank Palazzolo, Jr. ,  Ugo Zampieri

发明人： Bhaskar Chowdhuri ,  Kanwal Preet Singh Banga ,  Frank Palazzolo, Jr. ,  Ugo Zampieri

IPC分类号： G09G536

CPC分类号： G09G5/39 ,  G06F12/0875 ,  G09G2360/121 ,  G09G2360/122 ,  G09G2360/125 ,  G09G2360/128

摘要： The present invention relates to a system and method for accelerating graphics. The system includes a memory device for accelerating graphics operations within an electronic device. A memory controller is used for controlling pixel data transmitted to and from the memory device. A cache memory is electrically coupled to the memory and is dynamically configurable to a selected usable size to exchange an amount of pixel data having the selected usable size with the memory controller. The memory device may be an SDRAM. The cache memory may also comprise a plurality of usable memory areas or tiles.

摘要翻译： 本发明涉及加速图形的系统和方法。 该系统包括用于加速电子设备内的图形操作的存储装置。 存储器控制器用于控制传输到存储器件和从存储器件传输的像素数据。 高速缓冲存储器电耦合到存储器，并且可动态地配置为所选择的可用尺寸以将具有所选择的可用尺寸的像素数据量与存储器控制器交换。 存储器件可以是SDRAM。 高速缓冲存储器还可以包括多个可用的存储区域或瓦片。

公开(公告)号：US08041870B1

公开(公告)日：2011-10-18

申请号：US12758849

申请日：2010-04-13

申请人： Bhaskar Chowdhuri

发明人： Bhaskar Chowdhuri

IPC分类号： G06F13/36 ,  G06F13/362 ,  G06F3/00 ,  G06F5/00 ,  G06F13/00 ,  G06F12/00 ,  G06F13/14 ,  G06F13/38

CPC分类号： H04L47/20 ,  G06F13/364

摘要： An arbiter in a communication system including a plurality of request shapers in communication with a plurality of requestors. Each request shaper is configured to receive a request for access to a resource of the communication system, initially assign a priority level to the request upon receipt of the request, increase an age of the request, after increasing the age of the request, compare the age of the request to a delta period value associated with the respective requestor, and repeatedly increase the priority level of the request based on the comparison. Each of the plurality of requestors has a corresponding delta period value that is different from that of other ones of the plurality of requestors. An arbiter core is configured to grant one of the plurality of requestors access to the resource based on the priority level of each request and the age of each request.

摘要翻译： 一种通信系统中的仲裁器，包括与多个请求者通信的多个请求整形器。 每个请求整形器被配置为接收访问通信系统的资源的请求，在接收到请求之后，首先向请求分配优先级，在增加请求的年龄之后增加请求的年龄，比较 请求的年龄与相应请求者相关联的增量周期值，并且基于比较重复地增加请求的优先级。 多个请求者中的每一个具有与多个请求者中的其他请求者不同的对应的增量周期值。 仲裁器核心被配置为基于每个请求的优先级级别和每个请求的年龄来授予多个请求者中的一个对资源的访问。

公开(公告)号：US07698486B1

公开(公告)日：2010-04-13

申请号：US11390627

申请日：2006-03-28

申请人： Bhaskar Chowdhuri

发明人： Bhaskar Chowdhuri

IPC分类号： G06F13/36 ,  G06F13/362 ,  G06F3/00 ,  G06F5/00 ,  G06F13/00 ,  G06F12/00 ,  G06F13/14 ,  G06F13/38

CPC分类号： H04L47/20 ,  G06F13/364

摘要： An arbitration circuit for granting access to a shared resource among requestors comprises N request shapers, where N is an integer greater than one. An input unit receives a request from a requestor. An age unit assigns an age to the request and increases the age of the request when the requestor is not granted access to the shared resource. A priority unit assigns a priority level to each of the requests and selectively increases the priority level of the request based on the age of the respective one of the requests and a delta period of the request. An arbiter core receives the requests from the N request shapers and selectively grants access to the shared resource to each of the requestors corresponding to the requests based on the priority level and age of the requests. The delta period of one of the N request shapers is different than the delta period of another of the N request shapers.

摘要翻译： 用于授予对请求者之间的共享资源的访问的仲裁电路包括N个请求整形器，其中N是大于1的整数。 输入单元从请求者接收请求。 年龄单位为请求分配年龄，并且在请求者未被授权访问共享资源时增加请求的年龄。 优先级单元为每个请求分配优先级，并且基于请求中的相应一个请求的年龄和请求的增量周期选择性地增加请求的优先级。 仲裁器核心从N个请求整形器接收请求，并根据请求的优先级和年龄，选择性地向对应于请求的请求者授予对共享资源的访问。 N个请求整形器之一的增量周期与另外N个请求整形器的增量周期不同。

公开(公告)号：US08660617B1

公开(公告)日：2014-02-25

申请号：US11642817

申请日：2006-12-19

申请人： Raja Banerjea ,  Robert B. Ganton ,  Timothy J. Donovan ,  Bhaskar Chowdhuri

发明人： Raja Banerjea ,  Robert B. Ganton ,  Timothy J. Donovan ,  Bhaskar Chowdhuri

IPC分类号： H04M1/00

CPC分类号： H04W52/0229 ,  H04W52/0293 ,  Y02D70/142 ,  Y02D70/146

摘要： Power consumption is managed in a subscriber station of a communication system. The subscriber station is engaged in a sleep mode, including reducing a frequency of a system clock of the subscriber station. When the subscriber station receives, while in the sleep mode, a message having downlink transmission parameters while, the frequency of the system clock of the subscriber station is increased to process the message. After processing the message, the frequency of the system clock is reduced.

摘要翻译： 在通信系统的用户台中管理功耗。 用户台进入休眠模式，包括降低订户站的系统时钟的频率。 当用户站在休眠模式下接收到具有下行链路传输参数的消息时，增加用户站的系统时钟的频率以处理消息。 处理消息后，系统时钟的频率就会降低。

公开(公告)号：US08307139B1

公开(公告)日：2012-11-06

申请号：US13274674

申请日：2011-10-17

申请人： Bhaskar Chowdhuri

发明人： Bhaskar Chowdhuri

IPC分类号： G06F12/00 ,  G06F13/14 ,  G06F13/38 ,  G06F3/00 ,  G06F5/00 ,  G06F13/00 ,  G06F13/36 ,  G06F13/362

CPC分类号： H04L47/20 ,  G06F13/364

摘要： A communication system including a resource and an arbiter. The resource is shared among a plurality of requestors such that, at any given time, only one of the plurality of requestors has access to the resource. The arbiter is configured to receive a request from each of the plurality of requestors to access the resource, in which each request has a priority level associated with the request. The arbiter is further configured to age each request at a different rate relative to that associated with another request, and grant each requestor access to the resource based on i) the priority level and/or ii) the age of the request corresponding to the requestor.

摘要翻译： 包括资源和仲裁器的通信系统。 所述资源在多个请求者之间共享，使得在任何给定时间，所述多个请求者中只有一个访问该资源。 仲裁器被配置为从多个请求者中的每一个接收来自资源的请求，其中每个请求具有与请求相关联的优先级。 仲裁器被进一步配置为以相对于与另一请求相关联的速率的不同速率对每个请求进行老化，并且基于i）优先级和/或ii）与请求者相对应的请求的年龄来授予每个请求者对资源的访问权限 。

公开(公告)号：US07062582B1

公开(公告)日：2006-06-13

申请号：US10390431

申请日：2003-03-14

申请人： Bhaskar Chowdhuri

发明人： Bhaskar Chowdhuri

IPC分类号： G06F13/364 ,  G06F13/38

CPC分类号： H04L47/20 ,  G06F13/364

摘要： Various approaches grant access to a shared resource. An arbitration circuit includes request shapers that each receive a request from one of the requestors and assign a respective predetermined priority level and age to each of the requests. An arbiter core receives the requests and grants access to the shared resource to each of the requestors corresponding to the requests. The arbiter core includes a mask circuit that includes a plurality of mask registers each corresponding to a respective one of the priority levels. The age of a respective one of the requests increases when the corresponding one of the requestors is not granted access to the shared resource. The priority level of a respective one of the requests increases according to the age of the respective one of the requests.

摘要翻译： 各种方法授予对共享资源的访问权限。 仲裁电路包括请求整形器，每个请求整形器接收来自一个请求者的请求，并为每个请求分配相应的预定优先级和年龄。 仲裁核心接收请求，并授予对与请求对应的每个请求者的共享资源的访问。 仲裁核心包括掩模电路，其包括多个屏蔽寄存器，每个屏蔽寄存器对应于相应的一个优先级。 当对应的一个请求者未被授权访问共享资源时，请求中的相应一个请求的年龄增加。 相应一个请求的优先级根据请求的相应一个的年龄而增加。