公开(公告)号：US4566022A

公开(公告)日：1986-01-21

申请号：US461421

申请日：1983-01-27

申请人： Howard L. Kalter ,  Donald B. Kiley

发明人： Howard L. Kalter ,  Donald B. Kiley

IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/112 ,  H01L27/118 ,  H01L29/78

CPC分类号： H01L27/112

摘要： A transistor array arrangement for providing high-density semiconductor logic circuits in double polysilicon technology is described. Semiconductor, for example, FET, logic circuits have four independent but simultaneously accessible FET devices which are formed by intersecting sets of polysilicon gate lines. The four FET devices share a common first diffusion, for example a source, surrounded by four logically independent second diffusions, for example drains. A three-bit decode device is made which includes this array design.

摘要翻译： 描述了用于在双晶体技术中提供高密度半导体逻辑电路的晶体管阵列布置。 半导体，例如FET，逻辑电路具有四个独立但可同时访问的FET器件，它们由多个多晶硅栅极线的相交组合形成。 四个FET器件共享共同的第一扩散，例如由四个逻辑上独立的第二扩散（例如漏极）包围的源。 制作了一个包含这种阵列设计的三位解码器。

公开(公告)号：US4896054A

公开(公告)日：1990-01-23

申请号：US802923

申请日：1985-11-29

申请人： Donald B. Kiley

发明人： Donald B. Kiley

IPC分类号： G01R31/3185 ,  H03K3/037 ,  H03K3/356

CPC分类号： H03K3/356017 ,  G01R31/318552 ,  H03K3/0375 ,  H03K3/35606

摘要： This is related to a logic circuit which requires a double clocking latch during testing of the circuit to prevent race or flushing of the scan rings from occuring during the test mode and yet can be operated to capture and hold output data during the operation mode with stable data inputs. The preferred embodiment is a programmable latching circuit comprising a double ended cross coupled circuit having an input and an output and having first and second programmable legs and a third non-programmable leg with the first programmable leg cross coupled to the third leg and the second programmable leg being switchably cross coupled to the third leg.

摘要翻译： 这与逻辑电路有关，逻辑电路在测试电路期间需要双时钟锁存器，以防止扫描环在测试模式期间发生冲突或冲洗，并且可以在操作模式期间捕获和保持输出数据，并具有稳定的 数据输入。 优选实施例是可编程锁存电路，其包括具有输入和输出并具有第一和第二可编程脚的双端交叉耦合电路和具有第一可编程脚交叉耦合到第三支路的第三非可编程支路和第二可编程支路 腿可切换地与第三腿交叉耦合。