公开(公告)号：US06819321B1

公开(公告)日：2004-11-16

申请号：US09540615

申请日：2000-03-31

申请人： Hsien-Cheng Hsieh ,  Vladimir M. Pentkovski ,  Hsin-Chu Tsai

发明人： Hsien-Cheng Hsieh ,  Vladimir M. Pentkovski ,  Hsin-Chu Tsai

IPC分类号： G06F120

CPC分类号： G06T11/40 ,  G06T15/005

摘要： A method for processing 2D operations in a tiled graphics architecture is disclosed. A graphics controller processes both 3D primitives and 2D blit operations. The 3D primitives are sorted into bins using well-known techniques. When a 2D blit operation is to be processed, the 2D blit operation is also sorted into bins. The sorted 3D primitives and sorted 2D blit operations are then delivered to blit and rendering engines on a bin-by-bin basis. By sorting the 2D blit operations into bins along with the 3D primitives, there is no need to flush the bins (send primitives to rendering engines) whenever a 2D blit operation requires processing. The sorting of 2D blit operations into bins reduces the frequency of graphics cache misses and improves graphics memory bandwidth utilization, thereby improving overall computer system performance.

摘要翻译： 公开了一种在平铺图形架构中处理2D操作的方法。 图形控制器处理3D原始图像和2D图形操作。 使用众所周知的技术将3D原语分类到存储盒中。 当2D处理操作被处理时，2D blit操作也被分类成bin。 然后将排序的3D原语和排序的2D blit操作以逐位方式传送给blit和呈现引擎。 通过将2D blit操作与3D原语一起排列成bin，无论何时2D blit操作需要处理，都不需要将bin（发送原语发送到渲染引擎）。 将2D打印操作分类到存储空间可以降低图形缓存未命中的频率，并提高图形内存带宽利用率，从而提高计算机系统的整体性能。

公开(公告)号：US06885378B1

公开(公告)日：2005-04-26

申请号：US09675096

申请日：2000-09-28

申请人： Hsin-Chu Tsai ,  Subramaniam Maiyuran ,  Chung-Chi Wang

发明人： Hsin-Chu Tsai ,  Subramaniam Maiyuran ,  Chung-Chi Wang

IPC分类号： G06T15/00 ,  G09G5/36

CPC分类号： G06T15/005

摘要： According to one embodiment, a computer system is disclosed. The computer system includes a graphics accelerator and a graphics cache coupled to the graphics accelerator. The graphics cache stores texture data, color data and depth data.

摘要翻译： 根据一个实施例，公开了一种计算机系统。 计算机系统包括图形加速器和耦合到图形加速器的图形缓存。 图形缓存存储纹理数据，颜色数据和深度数据。

公开(公告)号：US06801208B2

公开(公告)日：2004-10-05

申请号：US09750750

申请日：2000-12-27

申请人： Jagganath Keshava ,  Vladimir Pentkovski ,  Subramaniam Maiyuran ,  Salvador Palanca ,  Hsin-Chu Tsai

发明人： Jagganath Keshava ,  Vladimir Pentkovski ,  Subramaniam Maiyuran ,  Salvador Palanca ,  Hsin-Chu Tsai

IPC分类号： G09G536

CPC分类号： G06F3/14 ,  G06F12/084 ,  G09G5/001 ,  G09G5/393 ,  G09G2330/021 ,  G09G2350/00

摘要： A system and method for cache sharing. The system is a microprocessor comprising a processor core and a graphics engine, each coupled to a cache memory. The microprocessor also includes a driver to direct how the cache memory is shared by the processor core and the graphics engine. The method comprises receiving a memory request from a graphics application program and determining whether a cache memory that may be shared between a processor core and a cache memory is available to be shared. If the cache memory is available to be shared, a first portion of the cache memory is allocated to the processor core and a second portion of the cache memory is allocated to the graphics engine. The method and microprocessor may be included in a computing device.

摘要翻译： 一种用于缓存共享的系统和方法。 该系统是包括处理器核心和图形引擎的微处理器，每个耦合到高速缓冲存储器。 微处理器还包括一个驱动程序，用于指示高速缓冲存储器如何由处理器核心和图形引擎共享。 该方法包括从图形应用程序接收存储器请求并确定可以在处理器核心和高速缓冲存储器之间共享的高速缓存存储器是否可共享。 如果高速缓冲存储器可用于共享，则高速缓冲存储器的第一部分被分配给处理器核心，高速缓冲存储器的第二部分被分配给图形引擎。 方法和微处理器可以包括在计算设备中。