Low word line to bit line short circuit standby current semiconductor
memory
    1.
    发明授权
    Low word line to bit line short circuit standby current semiconductor memory 失效
    低字线到位线短路待机电流半导体存储器

    公开(公告)号:US06046948A

    公开(公告)日:2000-04-04

    申请号:US114600

    申请日:1998-07-14

    申请人: Hua Zheng Yuan-Mou Su

    发明人: Hua Zheng Yuan-Mou Su

    摘要: A precharge circuit is operable during a standby mode to drive a word line to a low voltage level and one or more (pairs of) bit lines to a standby voltage level. The precharge circuit comprises a driver for driving the on or more bit lines to the stand by voltage level. The precharge circuit also includes a control circuit connected to a control input of the driver which control circuit receives the standby signal. The control circuit outputs a varying enable signal to the driver for varying the drive of the bit lines by the driver. The precharge circuit can include a first current limiting driver for driving the bit lines to the standby voltage level, and second driver, for driving the bit lines to the standby voltage level. The second driver has a greater switching speed, and a higher current driving capacity, than the first current limiting driver. Tie control circuit enables the second driver for a certain period of time in response to detecting an indication of a beginning of the standby mode of the standby signal.

    摘要翻译: 预充电电路在待机模式期间可操作以将字线驱动到低电压电平和一个或多个(对)位线到待机电压电平。 预充电电路包括用于通过电压电平驱动一个或多个位线到支架的驱动器。 预充电电路还包括连接到驱动器的控制输入端的控制电路,该控制电路接收待机信号。 控制电路向驾驶员输出变化的使能信号,以改变驾驶员对位线的驱动。 预充电电路可以包括用于将位线驱动到待机电压电平的第一限流驱动器和用于将位线驱动到待机电压电平的第二驱动器。 第二个驱动器具有比第一个限流驱动器更大的开关速度和更高的电流驱动能力。 响应于检测到待机信号的待机模式的开始的指示,带状控制电路使得第二驱动器能够持续一段时间。

    Circuit with regulated power supply for reducing memory device operating
power
    2.
    发明授权
    Circuit with regulated power supply for reducing memory device operating power 失效
    具有稳压电源的电路,用于减少存储器件的工作电源

    公开(公告)号:US5777940A

    公开(公告)日:1998-07-07

    申请号:US747699

    申请日:1996-11-12

    申请人: Yuan-Mou Su

    发明人: Yuan-Mou Su

    IPC分类号: G11C5/14 G11C11/417 G11C8/00

    CPC分类号: G11C5/147 G11C11/417

    摘要: In accordance with a preferred embodiment of the invention, the wordline turn on voltage in an SRAM array is suppressed (e.g., maintained at or below 4.5 volts). This is accomplished by connecting a regulated voltage supply output to the wordline. The regulated voltage supply has a transfer function such that the Vccr (the output of the regulated voltage supply) does not exceed a threshold such as 4.5 volts. For example, the transfer function may be: Vccr=Vcc for Vcc

    摘要翻译: 根据本发明的优选实施例,SRAM阵列中的字线导通电压被抑制(例如保持在或低于4.5伏)。 这是通过将稳压电源输出连接到字线来实现的。 调节电压源具有传递函数,使得Vccr(稳压电源的输出)不超过诸如4.5伏特的阈值。 例如,传递函数可以是:Vccr = Vcc,对于Vcc <4.5伏Vccr = 4.5伏,对于Vcc> / = 4.5伏,其中Vcc是电源电压。 如上所述,SRAM阵列中消耗的功率与所选择的字线电压成比例。 根据本发明,当Vcc超过4.5伏特时,功耗通常将不变。

    Method and system of adjusting DRAM refresh interval
    3.
    发明申请
    Method and system of adjusting DRAM refresh interval 审中-公开
    调整DRAM刷新间隔的方法和系统

    公开(公告)号:US20050036380A1

    公开(公告)日:2005-02-17

    申请号:US10640313

    申请日:2003-08-14

    申请人: Yuan-Mou Su

    发明人: Yuan-Mou Su

    IPC分类号: G11C11/406 G11C7/00

    摘要: A method of refreshing a DRAM chip. A working temperature is detected for the DRAM, and a corresponding refresh interval is decided accordingly. A refresh timing clock is generated with the corresponding refresh interval, and the DRAM is refreshed. The refresh interval decreases with increased working temperature, and increased with working temperature decrease.

    摘要翻译: 一种刷新DRAM芯片的方法。 检测DRAM的工作温度,相应地决定相应的刷新间隔。 利用相应的刷新间隔产生刷新定时时钟,并且刷新DRAM。 刷新间隔随着工作温度的升高而降低,随着工作温度的降低而增加。

    SRAM with fast write capability
    4.
    发明授权
    SRAM with fast write capability 失效
    SRAM具有快速写入能力

    公开(公告)号:US5943278A

    公开(公告)日:1999-08-24

    申请号:US755289

    申请日:1996-11-22

    申请人: Yuan-Mou Su

    发明人: Yuan-Mou Su

    IPC分类号: G11C11/419 G11C7/00

    CPC分类号: G11C11/419

    摘要: In accordance with a preferred embodiment of the invention, the write cycle of an SRAM column is increased. The SRAM column includes at least one SRAM cell connected to the bit line and the bit line complement of the column. Further, a pair of select transistors are located below the bottom SRAM cell, where one select transistor is connected to the bit line and the other is connected to the bit line complement. The select transistors select whether the respective bit line and bit line complement is deselected or selected. The SRAM column further includes a pair of load transistors connected between the bottom SRAM cell and the pair of select transistors, where one of the load transistors is connected to the bit line and the other load transistor is connected to said bit line complement. In operation, since the load transistors are located below the bottom cell, there is no DC current supplied by the load transistors to flow through the entire bit line and bit line complement length. Therefore, the voltage drop potential on the line is reduced which increases the write cycle speed.

    摘要翻译: 根据本发明的优选实施例,SRAM列的写入周期增加。 SRAM列包括连接到位线和列的位线补码的至少一个SRAM单元。 此外,一对选择晶体管位于底部SRAM单元下方,其中一个选择晶体管连接到位线,而另一个连接到位线补码。 选择晶体管选择是否取消选择相应的位线和位线补码。 SRAM列还包括连接在底部SRAM单元和一对选择晶体管之间的一对负载晶体管,其中一个负载晶体管连接到位线,另一个负载晶体管连接到所述位线补码。 在操作中,由于负载晶体管位于底部电池下方,所以不存在由负载晶体管提供的直流电流流过整个位线和位线补码长度。 因此,线路上的电压降电位降低,这增加了写入周期的速度。