Packet sending method and apparatus based on multi-link aggregation

    公开(公告)号:US10367723B2

    公开(公告)日:2019-07-30

    申请号:US15718623

    申请日:2017-09-28

    Abstract: Embodiments of the present invention provide a packet sending method, including: receiving a packet, where the packet carries priority information indicating a priority of the packet; selecting, according to a correspondence between packet priorities and component links in a link aggregation group, a component link corresponding to the priority of the packet, where the link aggregation group includes at least a first component link and a second component link, availability of the first component link is higher than availability of the second component link, and in the correspondence between packet priorities and component links, a first priority corresponds to the first component link, a second priority corresponds to at least one of the second component link and the first component link, and the first priority is higher than the second priority; and sending the packet on the selected component link.

    Chip and reading circuit for die ID in chip

    公开(公告)号:US10274534B2

    公开(公告)日:2019-04-30

    申请号:US15493369

    申请日:2017-04-21

    Abstract: A reading circuit for a die ID in a chip is provided. The reading circuit includes a chip damage detection circuit, a switch selector, a fuse controller, and a fuse device, where the fuse device stores the die ID; the fuse controller reads the die ID from the fuse device; the chip damage detection circuit detects whether a processor in the chip is capable of operating properly, so as to obtain a detection result, and notify the switch selector of the detection result; and when the detection result is that the processor is capable of operating properly, the switch selector connects the processor and the fuse controller; and when the detection result is that the processor is not capable of operating properly, the switch selector connects the fuse controller and a maintenance device that is located outside the chip.

    DRIVE CIRCUIT AND DISPLAY DEVICE
    4.
    发明申请

    公开(公告)号:US20250022409A1

    公开(公告)日:2025-01-16

    申请号:US18901998

    申请日:2024-09-30

    Inventor: Bo Liang Hu He

    Abstract: A drive circuit and a display device are provided. Changes in control electrode voltages of switching transistors do not couple a control electrode voltage of a drive transistor. The drive circuit may support different levels of image refresh frequencies at the same time, and implement seamless switching between different image refresh frequencies. The drive circuit may include a storage capacitor, the drive transistor, and the switching transistors. The drive transistor may be configured to control a drive current of the light-emitting diode, and the switching transistors may control the control electrode voltage of the drive transistor and compensate for a threshold voltage of the drive transistor. Other embodiments are described herein.

Patent Agency Ranking