公开(公告)号：US20230266941A1

公开(公告)日：2023-08-24

申请号：US18309269

申请日：2023-04-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Donglong Jiang ,  Zhenjiang Dong ,  Huan Xie ,  Chun Hang Lee

IPC: G06F7/485 ,  G06F5/01

CPC classification number: G06F7/485 ,  G06F5/012

Abstract: A splitting circuit included in a floating-point number calculation circuit splits a mantissa part of a first floating-point number and a mantissa part of a second floating-point number. An exponential processing circuit obtains a second number of shifted bits of each mantissa part obtained after splitting. A calculation circuit calculates a product of the mantissa part of the first floating-point number and the mantissa part of the second floating-point number based on each mantissa part obtained after splitting and the second number of shifted bits of each mantissa part obtained after splitting. The floating-point number calculation circuit can split a large bit-width floating-point number into small bit-width floating-point numbers, so that a small bit-width multiplier is used to calculate the large bit-width floating-point number.