公开(公告)号：US20240119114A1

公开(公告)日：2024-04-11

申请号：US18494455

申请日：2023-10-25

Applicant: Huawei Technologies Co., Ltd.

Inventor： Chun Hang Lee ,  Mingke Li ,  Yidong Zhang

IPC: G06F17/16

CPC classification number: G06F17/16

Abstract: A matrix multiplier includes an operation circuit and a controller. The operation circuit is coupled to the controller. The controller is configured to control the operation circuit to reuse a left fractal matrix Asr in n consecutive clock cycles, and control the operation circuit to use a right fractal matrix Brt in n right fractal matrices in each of the n consecutive clock cycles. The operation circuit is configured to multiply, in each of the n consecutive clock cycles, the left fractal matrix by the right fractal matrix in the n right fractal matrices to obtain n matrix operation results.

公开(公告)号：US20230266941A1

公开(公告)日：2023-08-24

申请号：US18309269

申请日：2023-04-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Donglong Jiang ,  Zhenjiang Dong ,  Huan Xie ,  Chun Hang Lee

IPC: G06F7/485 ,  G06F5/01

CPC classification number: G06F7/485 ,  G06F5/012

Abstract: A splitting circuit included in a floating-point number calculation circuit splits a mantissa part of a first floating-point number and a mantissa part of a second floating-point number. An exponential processing circuit obtains a second number of shifted bits of each mantissa part obtained after splitting. A calculation circuit calculates a product of the mantissa part of the first floating-point number and the mantissa part of the second floating-point number based on each mantissa part obtained after splitting and the second number of shifted bits of each mantissa part obtained after splitting. The floating-point number calculation circuit can split a large bit-width floating-point number into small bit-width floating-point numbers, so that a small bit-width multiplier is used to calculate the large bit-width floating-point number.

公开(公告)号：US11063695B2

公开(公告)日：2021-07-13

申请号：US16926094

申请日：2020-07-10

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yaron Ben-Arie ,  Chun Hang Lee ,  Genadiy Tsodik ,  Shimon Shilo ,  Doron Ezri

IPC: H04L1/02 ,  H04L1/00 ,  H04B7/0413

Abstract: The invention relates to an apparatus for selecting candidates in a K-Best algorithm of a MIMO decoder. The K-Best algorithm uses a layered structure comprising a first layer and subsequent layers. In each subsequent layer 2L candidates are selected by iteratively carrying out a selection step, wherein in the selection step the apparatus is configured to calculate and select at least two candidates having minimum distance values of a candidate group, and after each iteratively carried out selection step, the selected at least two candidates are sent to a further subsequent layer for iteratively generating a further candidate group of 2L candidates in the further subsequent layer.