公开(公告)号：US11250108B2

公开(公告)日：2022-02-15

申请号：US16869837

申请日：2020-05-08

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Zhenjiang Dong ,  Chio In Ieong ,  Hu Liu ,  Hai Chen

IPC: G06F17/16 ,  G06F7/42 ,  H03K19/20 ,  H03M7/30

Abstract: A matrix processing method includes: determining a quantity of non-zero elements in a to-be-processed matrix, where the to-be-processed matrix is a one-dimensional matrix; generating a distribution matrix of the to-be-processed matrix, where the distribution matrix is used to indicate a position of a non-zero element in the to-be-processed matrix; combining the quantity of non-zero elements, values of all non-zero elements in the to-be-processed matrix arranged sequentially, and the distribution matrix, to obtain a compressed matrix of the to-be-processed matrix.

公开(公告)号：US20200265108A1

公开(公告)日：2020-08-20

申请号：US16869837

申请日：2020-05-08

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Zhenjiang Dong ,  CHIO IN IEONG ,  Hu Liu ,  Hai Chen

IPC: G06F17/16 ,  G06F7/42 ,  H03K19/20 ,  H03M7/30

Abstract: A matrix processing method includes: determining a quantity of non-zero elements in a to-be-processed matrix, where the to-be-processed matrix is a one-dimensional matrix; generating a distribution matrix of the to-be-processed matrix, where the distribution matrix is used to indicate a position of a non-zero element in the to-be-processed matrix; combining the quantity of non-zero elements, values of all non-zero elements in the to-be-processed matrix arranged sequentially, and the distribution matrix, to obtain a compressed matrix of the to-be-processed matrix.

公开(公告)号：US20220114235A1

公开(公告)日：2022-04-14

申请号：US17560472

申请日：2021-12-23

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Zhenjiang Dong ,  CHIO IN IEONG ,  Hu Liu ,  Hai Chen

IPC: G06F17/16 ,  G06F7/42 ,  H03K19/20 ,  H03M7/30

Abstract: A matrix processing method performed by a graphics processing unit (GPU) includes: determining a plurality of non-zero elements in a to-be-processed matrix at a processor in the GPU; generating a distribution matrix of the to-be-processed matrix at the processor, where the distribution matrix comprises identities for indicating positions of the plurality of non-zero elements in the to-be-processed matrix; obtaining a target matrix from another matrix by using the distribution matrix at a logic circuit in the processor, where the target matrix comprises a plurality of target elements from the another matrix; and performing matrix processing on the plurality of non-zero elements and the target matrix to obtain an operation result at the processor.

公开(公告)号：US20230266941A1

公开(公告)日：2023-08-24

申请号：US18309269

申请日：2023-04-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Donglong Jiang ,  Zhenjiang Dong ,  Huan Xie ,  Chun Hang Lee

IPC: G06F7/485 ,  G06F5/01

CPC classification number: G06F7/485 ,  G06F5/012

Abstract: A splitting circuit included in a floating-point number calculation circuit splits a mantissa part of a first floating-point number and a mantissa part of a second floating-point number. An exponential processing circuit obtains a second number of shifted bits of each mantissa part obtained after splitting. A calculation circuit calculates a product of the mantissa part of the first floating-point number and the mantissa part of the second floating-point number based on each mantissa part obtained after splitting and the second number of shifted bits of each mantissa part obtained after splitting. The floating-point number calculation circuit can split a large bit-width floating-point number into small bit-width floating-point numbers, so that a small bit-width multiplier is used to calculate the large bit-width floating-point number.

公开(公告)号：US11734386B2

公开(公告)日：2023-08-22

申请号：US17560472

申请日：2021-12-23

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Zhenjiang Dong ,  Chio In Ieong ,  Hu Liu ,  Hai Chen

IPC: G06F17/16 ,  G06F7/42 ,  H03K19/20 ,  H03M7/30

CPC classification number: G06F17/16 ,  G06F7/42 ,  H03K19/20 ,  H03M7/30

Abstract: A matrix processing method performed by a graphics processing unit (GPU) includes: determining a plurality of non-zero elements in a to-be-processed matrix at a processor in the GPU; generating a distribution matrix of the to-be-processed matrix at the processor, where the distribution matrix comprises identities for indicating positions of the plurality of non-zero elements in the to-be-processed matrix; obtaining a target matrix from another matrix by using the distribution matrix at a logic circuit in the processor, where the target matrix comprises a plurality of target elements from the another matrix; and performing matrix processing on the plurality of non-zero elements and the target matrix to obtain an operation result at the processor.