公开(公告)号：US08885785B2

公开(公告)日：2014-11-11

申请号：US14013895

申请日：2013-08-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xuekun Zhang ,  Jindi Zhang ,  Bo Yu ,  Faji Yin

IPC: H04L7/00 ,  H04L7/02

CPC classification number: H04L7/02 ,  H03L7/00 ,  H04L7/0083

Abstract: Embodiments of the present invention disclose a CDR circuit and a terminal, where the CDR circuit is configured to perform clock synchronization in a terminal with EEE function, and the CDR circuit includes: a phase detector, a first phase signal selector, a loop filter, a numerical controlled oscillator, a second phase signal selector, a phase signal generator, and a state machine. In the embodiments of the present invention, after the terminal enters a REFRESH state from a QUIET state, the CDR circuit can implement clock synchronization with a peer end without waiting for the loop filter and the numerical controlled oscillator to be converged, but the phase signal generator generates a phase signal satisfying a preset clock synchronization condition, and the second phase signal selector selects the phase signal satisfying the preset clock synchronization condition as the phase selection signal of the CDR.

Abstract translation: 本发明的实施例公开了CDR电路和终端，其中CDR电路被配置为在具有EEE功能的终端中执行时钟同步，并且CDR电路包括：相位检测器，第一相位信号选择器，环路滤波器， 数控振荡器，第二相位信号选择器，相位信号发生器和状态机。 在本发明的实施例中，在终端从QUIET状态进入REFRESH状态之后，CDR电路可以实现与对端的时钟同步，而不必等待环路滤波器并且数控振荡器被收敛，而相位信号 发生器产生满足预设时钟同步状态的相位信号，第二相位信号选择器选择满足预设时钟同步条件的相位信号作为CDR的相位选择信号。