Boost power conversion circuit
    1.
    发明授权

    公开(公告)号:US11025163B2

    公开(公告)日:2021-06-01

    申请号:US16913219

    申请日:2020-06-26

    Abstract: A boost power conversion circuit includes an inductor, a first switch module, a second switch module, a first unilateral conduction component, a second unilateral conduction component, a flying capacitor, an upper bus capacitor, a lower bus capacitor, and a third unilateral conduction component. The power supply, the inductor, the first switch module, and the second switch module are connected in series to form a loop. The first unilateral conduction component, the second unilateral conduction component, the upper bus capacitor and the lower bus capacitor are connected in series. The flying capacitor is electrically connected between a reverse cut-off end of the first unilateral conduction component and a forward conduction end of the second unilateral conduction component. The third unilateral conduction component is configured to clamp a voltage stress of the second switch module to a lower-bus voltage.

    Service Processing Method and Apparatus, Terminal Device, and Chip

    公开(公告)号:US20240031852A1

    公开(公告)日:2024-01-25

    申请号:US18256451

    申请日:2021-12-08

    CPC classification number: H04W24/10 H04B7/0413 H04B7/0802 H04W88/06

    Abstract: This application provides a service processing method and apparatus, a terminal device, and a chip, and relates to the field of communication technologies. When the terminal device carries a primary card and a secondary card, the secondary card uses one or more antennas by default to process an uplink/downlink transmission service. When the primary card is triggered to perform neighboring cell measurement (e.g., inter-frequency inter-RAT measurement), and a measurement band is the same as an operating band of the secondary card, the primary card may select an antenna different from an antenna used by the secondary card to perform neighboring cell measurement.

    Channel Arbitration Method and Apparatus
    4.
    发明公开

    公开(公告)号:US20230396992A1

    公开(公告)日:2023-12-07

    申请号:US18249697

    申请日:2021-08-27

    CPC classification number: H04W8/245 H04W8/183 H04W72/12

    Abstract: Embodiments of this application disclose a channel arbitration method and an apparatus. After receiving an uplink grant for a first SIM card, a physical layer scheduler of a terminal device configures a transmission service priority of the first SIM card in a front-end arbiter as a first predicted priority, and configures PUSCH transmission information for the front-end arbiter based on the uplink grant, where if packeting for uplink scheduling is completed before an arbitration time point, the transmission service priority of the first SIM card is updated to a service priority of a MAC layer; the front-end arbiter arbitrates a transmission service of the first SIM card based on the PUSCH transmission information and the transmission service priority; and further, if the first SIM card is performing a voice service and the arbitration continuously fails, fallback to a DSDS 2.0 mode is triggered.

    Display method of terminal device and terminal device

    公开(公告)号:US10254950B2

    公开(公告)日:2019-04-09

    申请号:US15314260

    申请日:2014-05-30

    Inventor: Bo Yu Jianbin Qiu

    Abstract: A display method of a terminal device and a terminal device is provided. The display method of a terminal device includes: a framework layer sends a first touch point data; an application layer sends instruction information used to instruct to transfer slide drawing control rights to the framework layer and a generated display list to the framework layer after the application layer determines that the terminal device enters a sliding state according to acquired first touch point data; and the framework layer acquires second touch point data from a shared memory according to the instruction information, and draws an image according to the second touch point data and the display list. In this way, in an operation with repetitive image composition, the slide drawing control rights are transferred from an application module to a framework module, improving a response speed of a terminal system.

    CDR circuit and terminal
    7.
    发明授权
    CDR circuit and terminal 有权
    CDR电路和终端

    公开(公告)号:US08885785B2

    公开(公告)日:2014-11-11

    申请号:US14013895

    申请日:2013-08-29

    CPC classification number: H04L7/02 H03L7/00 H04L7/0083

    Abstract: Embodiments of the present invention disclose a CDR circuit and a terminal, where the CDR circuit is configured to perform clock synchronization in a terminal with EEE function, and the CDR circuit includes: a phase detector, a first phase signal selector, a loop filter, a numerical controlled oscillator, a second phase signal selector, a phase signal generator, and a state machine. In the embodiments of the present invention, after the terminal enters a REFRESH state from a QUIET state, the CDR circuit can implement clock synchronization with a peer end without waiting for the loop filter and the numerical controlled oscillator to be converged, but the phase signal generator generates a phase signal satisfying a preset clock synchronization condition, and the second phase signal selector selects the phase signal satisfying the preset clock synchronization condition as the phase selection signal of the CDR.

    Abstract translation: 本发明的实施例公开了CDR电路和终端,其中CDR电路被配置为在具有EEE功能的终端中执行时钟同步,并且CDR电路包括:相位检测器,第一相位信号选择器,环路滤波器, 数控振荡器,第二相位信号选择器,相位信号发生器和状态机。 在本发明的实施例中,在终端从QUIET状态进入REFRESH状态之后,CDR电路可以实现与对端的时钟同步,而不必等待环路滤波器并且数控振荡器被收敛,而相位信号 发生器产生满足预设时钟同步状态的相位信号,第二相位信号选择器选择满足预设时钟同步条件的相位信号作为CDR的相位选择信号。

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