公开(公告)号：US20210224119A1

公开(公告)日：2021-07-22

申请号：US17223907

申请日：2021-04-06

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jun Wang ,  Xuefeng Han ,  Handong Ye

IPC: G06F9/50 ,  G06F1/324

Abstract: Adjusting an operating frequency of a CPU includes setting the operating frequency for a current operating cycle based on a CPU load in a prior operating cycle and a target CPU load. A current CPU load associated with the current processing cycle is detected. The CPU operating frequency is adjusted to a new operating frequency based on a difference between the target CPU load and the current CPU load. The operating frequency is adjusted based on minimizing the difference between the target CPU load and the detected load. A CPU load error is determined based on the current CPU load and the target CPU load. The target CPU load is adjusted based on the determined CPU load error and a threshold load error. A prediction is generated on whether to perform a new adjustment of the operating frequency of the CPU prior to expiration of a threshold time duration.

公开(公告)号：US12124883B2

公开(公告)日：2024-10-22

申请号：US17223907

申请日：2021-04-06

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jun Wang ,  Xuefeng Han ,  Handong Ye

IPC: G06F9/50 ,  G06F1/324

CPC classification number: G06F9/505 ,  G06F1/324

Abstract: Adjusting an operating frequency of a CPU includes setting the operating frequency for a current operating cycle based on a CPU load in a prior operating cycle and a target CPU load. A current CPU load associated with the current processing cycle is detected. The CPU operating frequency is adjusted to a new operating frequency based on a difference between the target CPU load and the current CPU load. The operating frequency is adjusted based on minimizing the difference between the target CPU load and the detected load. A CPU load error is determined based on the current CPU load and the target CPU load. The target CPU load is adjusted based on the determined CPU load error and a threshold load error. A prediction is generated on whether to perform a new adjustment of the operating frequency of the CPU prior to expiration of a threshold time duration.

公开(公告)号：US20140249796A1

公开(公告)日：2014-09-04

申请号：US14279537

申请日：2014-05-16

Applicant: Huawei Technologies Co., Ltd.

Inventor： Handong Ye ,  Peng Zhao ,  Senhuo Zheng ,  Jiong Cao

IPC: G06F9/455

CPC classification number: G06F9/455 ,  G06F8/30 ,  G06F8/53 ,  G06F9/4552 ,  G06F17/5022 ,  G06F2217/86

Abstract: The present invention discloses a simulator generation method and apparatus, relating to the field of simulator generation, which are used to implement rapid portability and high efficiency of a simulator. The solutions in the present invention are applicable to simulator generation.

Abstract translation: 本发明公开了一种用于实现模拟器的快速便携性和高效率的模拟器生成领域的模拟器生成方法和装置。 本发明的解决方案适用于模拟器生成。

公开(公告)号：US09753752B2

公开(公告)日：2017-09-05

申请号：US14279537

申请日：2014-05-16

Applicant: Huawei Technologies Co., Ltd.

Inventor： Handong Ye ,  Peng Zhao ,  Senhuo Zheng ,  Jiong Cao

IPC: G06F9/455 ,  G06F9/44 ,  G06F9/45 ,  G06F17/50

CPC classification number: G06F9/455 ,  G06F8/30 ,  G06F8/53 ,  G06F9/4552 ,  G06F17/5022 ,  G06F2217/86

Abstract: The present invention discloses a simulator generation method and apparatus, relating to the field of simulator generation, which are used to implement rapid portability and high efficiency of a simulator. The solutions in the present invention are applicable to simulator generation.

公开(公告)号：US09703905B2

公开(公告)日：2017-07-11

申请号：US14142567

申请日：2013-12-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： Handong Ye ,  Jiong Cao ,  Xiaochun Ye ,  Da Wang

IPC: G06F17/50 ,  G06F11/26

CPC classification number: G06F17/5022 ,  G06F11/261

Abstract: The present invention provides a method and a system for simulating multiple processors in parallel, and a scheduler. In this embodiment, the scheduler maps debug interface information of a to-be-simulated processor requiring debugging onto the scheduler during parallel simulation of multiple processors, so that the scheduler is capable of debugging, by using a master thread, the to-be-simulated processor requiring debugging via a debug interface of the to-be-simulated processor requiring debugging pointed by the debug interface information, thereby implementing debugging during parallel simulation of multiple processors.