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    Method and system for simulating multiple processors in parallel and scheduler
    2.
    发明授权
    Method and system for simulating multiple processors in parallel and scheduler 有权

    公开(公告)号：US09703905B2

    公开(公告)日：2017-07-11

    申请号：US14142567

    申请日：2013-12-27

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Handong Ye ,  Jiong Cao ,  Xiaochun Ye ,  Da Wang

    IPC: G06F17/50 ,  G06F11/26

    CPC classification number: G06F17/5022 ,  G06F11/261

    Abstract: The present invention provides a method and a system for simulating multiple processors in parallel, and a scheduler. In this embodiment, the scheduler maps debug interface information of a to-be-simulated processor requiring debugging onto the scheduler during parallel simulation of multiple processors, so that the scheduler is capable of debugging, by using a master thread, the to-be-simulated processor requiring debugging via a debug interface of the to-be-simulated processor requiring debugging pointed by the debug interface information, thereby implementing debugging during parallel simulation of multiple processors.

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