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公开(公告)号：US20230411486A1
公开(公告)日：2023-12-21
申请号：US18460216
申请日：2023-09-01
发明人： Gilberto Curatola , Qilong Bao , Qimeng Jiang , Gaofei Tang , Hanxing Wang
IPC分类号： H01L29/47 , H01L29/20 , H01L29/778
CPC分类号： H01L29/475 , H01L29/2003 , H01L29/7786
摘要： The disclosure relates to a Gallium Nitride power transistor, comprising: a buffer layer; and a barrier layer having a top side, a bottom side, the bottom side facing the buffer layer, the bottom side of the barrier layer is placed on the buffer layer; an interlayer interposed between a p-type doped Gallium Nitride layer and a metal gate layer, the interlayer is made of a III-V compound semiconductor comprising a combination of at least one group III element with at least one group V element, the p-type doped Gallium Nitride layer is placed on the top side of the barrier layer, the metal gate layer is electrically connected to the p-type doped Gallium Nitride layer via the interlayer to form a rectifying metal-semiconductor junction with the p-type doped Gallium Nitride layer.
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公开(公告)号：US11791627B2
公开(公告)日：2023-10-17
申请号：US17863128
申请日：2022-07-12
发明人： Qimeng Jiang , Yushan Li , Hanxing Wang
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An ESD protection circuit is provided, including a negative ESD protection module and a positive ESD protection module, where the negative ESD protection module includes a first resistor, a charging capacitor, a first field effect transistor, and a second field effect transistor, and the positive ESD protection module includes a fourth field effect transistor. When a negative ESD event occurs, there is a comparatively large transient voltage at a gate of a P-type enhanced GaN power device relative to a source of the P-type enhanced GaN power device. Therefore, a displacement current from the source to the gate of the P-type enhanced GaN power device is generated on the charging capacitor. A voltage drop generated by the displacement current on the first resistor may enable the first field effect transistor and the second field effect transistor to form a path when the first field effect transistor is turned on.
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公开(公告)号：US11411396B2
公开(公告)日：2022-08-09
申请号：US17211515
申请日：2021-03-24
发明人： Qimeng Jiang , Yushan Li , Hanxing Wang
IPC分类号： H02H9/04
摘要： An ESD protection circuit is provided, including a negative ESD protection module and a positive ESD protection module, where the negative ESD protection module includes a first resistor, a charging capacitor, a first field effect transistor, and a second field effect transistor, and the positive ESD protection module includes a fourth field effect transistor. When a negative ESD event occurs, there is a comparatively large transient voltage at a gate of a P-type enhanced GaN power device relative to a source of the P-type enhanced GaN power device. Therefore, a displacement current from the source to the gate of the P-type enhanced GaN power device is generated on the charging capacitor. A voltage drop generated by the displacement current on the first resistor may enable the first field effect transistor and the second field effect transistor to form a path when the first field effect transistor is turned on.
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4.发明公开公开(公告)号：US20240204094A1
公开(公告)日：2024-06-20
申请号：US18592325
申请日：2024-02-29
发明人： Gaofei Tang , Daisuke Ueda , Hui Sun , Qilong Bao , Hanxing Wang
IPC分类号： H01L29/778 , H01L29/20 , H01L29/66
CPC分类号： H01L29/7786 , H01L29/2003 , H01L29/66462
摘要： A gallium nitride component includes a gallium nitride layer, a barrier layer on a surface of a side of the gallium nitride layer, and a gate on a side that is of the barrier layer and that is away from the gallium nitride layer. The gallium nitride layer has a gate region and a non-gate region outside the gate region. The barrier layer is located in the gate region and the non-gate region. A size of the barrier layer located in the gate region is greater than a size of the barrier layer located in the non-gate region, and aluminum concentration on a side that is of the barrier layer located in the gate region and that faces the gallium nitride layer is greater than aluminum concentration on a side that is of the barrier layer located in the gate region and that faces the gate.
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公开(公告)号：US20220344485A1
公开(公告)日：2022-10-27
申请号：US17727221
申请日：2022-04-22
发明人： Qilong Bao , Qimeng Jiang , Gaofei Tang , Hanxing Wang , Boning Huang , Zhaozheng Hou
IPC分类号： H01L29/45 , H03K17/041 , H01L29/778 , H01L29/66 , H01L29/40 , H01L29/417
摘要： A gallium nitride (GaN) device, where a drain of the GaN device includes a p-type (P-GaN) layer and a drain metal. The drain metal includes a plurality of first structural intervals and a plurality of second structural intervals. The plurality of first structural intervals and the plurality of second structural intervals are alternately distributed in the gate width direction. In this way, the drain metal implements local injection of holes for the device in the first structural intervals, and forms ohmic contact in the second structural intervals, implementing current conduction from a drain to a source of the device.
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