公开(公告)号：US20240405114A1

公开(公告)日：2024-12-05

申请号：US18736138

申请日：2024-06-06

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Gilberto Curatola

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66

Abstract: A member includes a buffer layer made of GaN. The member is characterized in that the member includes a source layer arranged on top of the buffer layer, and the source layer made of n-doped GaN. The member includes a first barrier layer made of Al—GaN arranged over the buffer layer and a first gate layer made of p-doped GaN arranged over the first barrier layer, where the first barrier layer and the first gate layer are arranged adjacent the source layer on one side. The member includes a second barrier layer made of Al—GaN arranged over the buffer layer and a second gate layer made of p-doped GaN arranged over the second barrier layer, where the second barrier layer and the second gate layer are arranged adjacent the source layer on another side. The member enables an independent optimization of the two-dimensional electron gas characteristics and the threshold voltage.

公开(公告)号：US20230411486A1

公开(公告)日：2023-12-21

申请号：US18460216

申请日：2023-09-01

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Gilberto Curatola ,  Qilong Bao ,  Qimeng Jiang ,  Gaofei Tang ,  Hanxing Wang

IPC: H01L29/47 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/475 ,  H01L29/2003 ,  H01L29/7786

Abstract: The disclosure relates to a Gallium Nitride power transistor, comprising: a buffer layer; and a barrier layer having a top side, a bottom side, the bottom side facing the buffer layer, the bottom side of the barrier layer is placed on the buffer layer; an interlayer interposed between a p-type doped Gallium Nitride layer and a metal gate layer, the interlayer is made of a III-V compound semiconductor comprising a combination of at least one group III element with at least one group V element, the p-type doped Gallium Nitride layer is placed on the top side of the barrier layer, the metal gate layer is electrically connected to the p-type doped Gallium Nitride layer via the interlayer to form a rectifying metal-semiconductor junction with the p-type doped Gallium Nitride layer.

公开(公告)号：US20240079233A1

公开(公告)日：2024-03-07

申请号：US18509050

申请日：2023-11-14

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Gilberto Curatola ,  Marco Silvestri

IPC: H01L21/02 ,  H01L27/06 ,  H01L29/24 ,  H01L29/78 ,  H01L29/812 ,  H01L29/872 ,  H01L31/032 ,  H01L31/108

CPC classification number: H01L21/02565 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02496 ,  H01L21/02576 ,  H01L21/02617 ,  H01L27/0629 ,  H01L29/24 ,  H01L29/78 ,  H01L29/812 ,  H01L29/872 ,  H01L31/032 ,  H01L31/108

Abstract: A member is provided which includes a silicon base substrate layer, a transition layer arranged over the silicon base substrate layer, and a gallium nitride (GaN) buffer layer arranged over the transition layer. The member further includes a gallium oxide layer. The member is beneficial for co-integration of ultra-wide-bandgap technology with wide bandgap technology, such as by using the gallium oxide layer with the gallium nitride buffer layer on cheap silicon substrates, such as the silicon base substrate layer. Therefore, the member provides access to establish the gallium nitride buffer layer (or gallium nitride) on the silicon base substrate layer (or silicon production lines) with improved thermal conductivity and higher electrical performance.

公开(公告)号：US20230335597A1

公开(公告)日：2023-10-19

申请号：US18338125

申请日：2023-06-20

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Gilberto Curatola

IPC: H01L29/20 ,  H01L29/812 ,  H01L29/06 ,  H01L29/47 ,  H01L29/15

CPC classification number: H01L29/2003 ,  H01L29/812 ,  H01L29/0661 ,  H01L29/0611 ,  H01L29/475 ,  H01L29/157

Abstract: The present disclosure relates to a Gallium Nitride (GaN) power transistor, comprising: a buffer layer; a barrier layer deposited on the buffer layer, wherein a gate region is formed on top of the barrier layer; a p-type doped GaN layer deposited on the barrier layer at the gate region; and a metal gate layer deposited on top of the p-type doped GaN layer, wherein the metal gate layer is contacting the p-type doped GaN layer to form a Schottky barrier, wherein a thickness of the p-type doped GaN layer, a metal type of the metal gate layer and a p-type doping concentration of the p-type doped GaN layer are based on a known relationship of a pGaN Schottky gate depletion region thickness with respect to a p-type doping concentration and a gate metal type.