公开(公告)号：US20240249054A1

公开(公告)日：2024-07-25

申请号：US18426293

申请日：2024-01-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Zezhong Wang ,  Yu Huang ,  Weiwei Zhang ,  Naixing Wang ,  Pengju Li

IPC: G06F30/333 ,  G06F30/323

CPC classification number: G06F30/333 ,  G06F30/323

Abstract: A method for designing a test circuit, includes determining a feature of a to-be-tested circuit based on data representing the to-be-tested circuit. The method further includes determining switch distribution for the to-be-tested circuit based on the feature of the to-be-tested circuit. The switch distribution represents distribution, in a two-dimensional switch matrix circuit, of a plurality of switches that are in a test circuit and that are coupled to a plurality of scan chains of the to-be-tested circuit. The switch matrix circuit includes a plurality of rows and a plurality of columns, any one of the plurality of rows has at least one of the plurality of switches, and any one of the plurality of columns has at least one of the plurality of switches.

公开(公告)号：US20240125850A1

公开(公告)日：2024-04-18

申请号：US18397481

申请日：2023-12-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： Huiling Zhen ,  Miaohui Chen ,  Mingxuan Yuan ,  Naixing Wang ,  Wanqian Luo ,  Yu Huang

IPC: G01R31/3181 ,  G01R31/3177 ,  G01R31/3183 ,  G01R31/3185

CPC classification number: G01R31/31813 ,  G01R31/3177 ,  G01R31/318342 ,  G01R31/318544

Abstract: An automatic test pattern generation-based circuit verification method, comprises: determining a to-be-detected first logic cone from a fan-out logic cone corresponding to the target line; determining, based on the first logic cone, a to-be-detected second logic cone from a fan-in logic cone corresponding to the target line; generating a first CNF based on the first logic cone and the second logic cone, and detecting the target line by using the first CNF to obtain a first detection result; and if the first logic cone is a partial region in the fan-out logic cone, and the first detection result meets a first specified condition corresponding to the first logic cone, determining a first verification result of the target line based on the first detection result.