公开(公告)号：US20250132750A1

公开(公告)日：2025-04-24

申请号：US19001699

申请日：2024-12-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Theng Tee Yeo ,  Sheng Chen

IPC: H03H11/04 ,  H04B1/40

Abstract: A discrete-time filter includes a transconductance circuit, a switched-capacitor filter circuit, a first sampling capacitor, a second sampling capacitor, and a switch, where an output end of the transconductance circuit is coupled to a first node through the switched-capacitor filter circuit; both a first end of the first sampling capacitor and a first terminal of the switch are coupled to the first node; and both a second terminal of the switch and a second end of the first sampling capacitor are grounded. The second sampling capacitor is coupled to the switch such that sampling is implemented and negative feedback is provided by switching connection ends of the switch to adjust a feedback coefficient.

公开(公告)号：US20230336163A1

公开(公告)日：2023-10-19

申请号：US18338893

申请日：2023-06-21

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sheng Chen ,  Theng Tee Yeo

IPC: H03K3/012 ,  H03K3/037 ,  H03K19/20

CPC classification number: H03K3/012 ,  H03K3/037 ,  H03K19/20

Abstract: A multi-phase clock generation circuit is configured to generate a multi-phase non-overlapping clock signal and includes a loop structure, where input ends and output ends of a plurality of logic gates are electrically coupled head to tail to form the loop structure; and a plurality of latches configured to latch signals at the input ends of the logic gates. The multi-phase clock generation circuit performs a logical operation based on selection signals and clock signals that are received at the logic gates, latches data of upper-stage logic gates that is received at logic gates in a loop through the latches, and outputs multi-phase non-overlapping clock signals through the output ends of the logic gates.

公开(公告)号：US20240250701A1

公开(公告)日：2024-07-25

申请号：US18623457

申请日：2024-04-01

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shuqi Wang ,  Theng Tee Yeo ,  Weihua Li

IPC: H04B1/00 ,  H04B1/3877

CPC classification number: H04B1/006 ,  H04B1/3877

Abstract: A radio frequency front end module (FEM) coupled to a radio frequency transceiver circuit and includes a first port coupled to a sending branch and a receiving branch through a switching system, and a second port coupled to the sending branch and the receiving branch through the switching system. The first port supports signal transmission of a first frequency band, and the second port supports signal transmission of a second frequency band. The receiving branch supports receiving processing of signals of the first frequency band and the second frequency band. The sending branch supports sending processing of signals of the first frequency band and the second frequency band. The switching module is configured to selectively transmit a signal either processed by the sending branch to the first port or the second port, or received by the first port or a signal received by the second port to the receiving branch.