Read latency reduction method and apparatus

    公开(公告)号:US11210210B2

    公开(公告)日:2021-12-28

    申请号:US16884158

    申请日:2020-05-27

    Abstract: A read latency reduction method includes receiving a read request sent by a host, where the read request includes location indication information of requested data, obtaining, from read voltage management information based on a first physical location indicated by the location indication information, a read voltage corresponding to a first storage area in which the first physical location is located, the flash array includes a plurality of storage areas, the read voltage management information includes a correspondence between a storage area and a read voltage, and the read voltage in the read voltage management information is dynamically updated, and obtaining the requested data based on the read voltage corresponding to the first storage area, and sending the requested data to the host.

    Read Latency Reduction Method and Apparatus
    2.
    发明申请

    公开(公告)号:US20200285575A1

    公开(公告)日:2020-09-10

    申请号:US16884158

    申请日:2020-05-27

    Abstract: A read latency reduction method includes receiving a read request sent by a host, where the read request includes location indication information of requested data, obtaining, from read voltage management information based on a first physical location indicated by the location indication information, a read voltage corresponding to a first storage area in which the first physical location is located, the flash array includes a plurality of storage areas, the read voltage management information includes a correspondence between a storage area and a read voltage, and the read voltage in the read voltage management information is dynamically updated, and obtaining the requested data based on the read voltage corresponding to the first storage area, and sending the requested data to the host.

    Scheduling regions of a field programmable gate array as virtual devices

    公开(公告)号:US11429447B2

    公开(公告)日:2022-08-30

    申请号:US16984956

    申请日:2020-08-04

    Inventor: Tian Xia Zhe Liu

    Abstract: A resource scheduling method, to improve resource utilization of a field-programmable gate array (FPGA) device, includes receiving a resource scheduling request from a host, where the resource scheduling request requests to schedule a partial region (PR) on the FPGA device to serve a first virtual device (VD) of the host, the FPGA device includes N PRs, the host includes M VDs, each of the M VDs is configured corresponding to one virtual machine (VM), the first VD is one of the M VDs, and both N and M are integers greater than one, obtaining context content of the first VD based on the resource scheduling request, determining a target PR in the N PRs, and deploying the context content of the first VD in the target PR.

    Data Writing Method and Processing System

    公开(公告)号:US20250013535A1

    公开(公告)日:2025-01-09

    申请号:US18891094

    申请日:2024-09-20

    Abstract: A data writing method includes obtaining first to-be-written data, where the first to-be-written data is data to be written into a first memory in the processing system; determining a first codeword length based on a first redundancy ratio corresponding to the first memory; performing ECC encoding on the first to-be-written data based on the first codeword length, to obtain first redundant data, where the first redundancy ratio is equal to a ratio of a data bit included in the first to-be-written data to a redundant bit included in the first redundant data; obtaining a memory type of the first memory; and writing the first to-be-written data and the first redundant data into the first memory based on the memory type.

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