公开(公告)号：US12260248B2

公开(公告)日：2025-03-25

申请号：US16800799

申请日：2020-02-25

Applicant: Huawei Technologies Co., Ltd.

Inventor： Tal Horowitz ,  Uri Weiser ,  Zuguang Wu ,  Huibin Luo ,  Yoni Choukroun

IPC: G06F9/48 ,  G06F9/38 ,  G06F15/80

Abstract: A multi-thread systolic array includes a plurality of processing elements, each including a processor. Each of the processing elements is configured to: receive a plurality of first inputs from a respective first input source; receive a plurality of second inputs from a respective second input source; the plurality of first inputs and the plurality of second inputs being arranged as a plurality of pairs corresponding to a plurality of threads; schedule, for each operation cycle of the processor, a certain thread of the plurality of threads; and execute a computation operation for the certain thread.

公开(公告)号：US10417005B2

公开(公告)日：2019-09-17

申请号：US15700488

申请日：2017-09-11

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Uri Weiser ,  Tal Horowitz ,  Jintang Wang

IPC: G06F15/76 ,  G06F9/50 ,  G06F9/312 ,  G06F9/38 ,  G06F15/80 ,  G06F15/17

Abstract: A data processing apparatus is provided comprising a front-end interface electronically coupled to a main processor. The front-end interface is configured to receive data stored in a repository, in particular an external storage and/or a network, determine whether the data is a single-access data or a multiple-access data by analyzing an access parameter designating the data, route the multiple-access data for processing by the main processor, and route the single-access data for pre-processing by the front-end interface and routing results of the pre-processing to the main processor.