公开(公告)号：US11343650B1

公开(公告)日：2022-05-24

申请号：US17131753

申请日：2020-12-23

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yoni Choukroun ,  Michael Zibulevsky

IPC: H04W4/029 ,  G06N20/00 ,  H04L67/52 ,  G06K9/62

Abstract: An unconstrained saddle point of a function is obtained by computing a combination of a first subspace for minimization, and a second subspace for maximization. A combination of a current location including a first and second current location within the first and second subspace is iteratively selected. From the current location, a combination of a step-size including a first and second step-size along a first and second direction of the first and second subspace, is computed. The first and second step-size is to a next first and second location within the first and second subspace. The current location is set to a next location including the next first and second location. The combination of the first and second subspace is according to the next location. The iterations terminate when the next location meets a requirement denoting the unconstrained saddle point. The location indicating the unconstrained saddle point is provided.

公开(公告)号：US12260248B2

公开(公告)日：2025-03-25

申请号：US16800799

申请日：2020-02-25

Applicant: Huawei Technologies Co., Ltd.

Inventor： Tal Horowitz ,  Uri Weiser ,  Zuguang Wu ,  Huibin Luo ,  Yoni Choukroun

IPC: G06F9/48 ,  G06F9/38 ,  G06F15/80

Abstract: A multi-thread systolic array includes a plurality of processing elements, each including a processor. Each of the processing elements is configured to: receive a plurality of first inputs from a respective first input source; receive a plurality of second inputs from a respective second input source; the plurality of first inputs and the plurality of second inputs being arranged as a plurality of pairs corresponding to a plurality of threads; schedule, for each operation cycle of the processor, a certain thread of the plurality of threads; and execute a computation operation for the certain thread.

公开(公告)号：US10735141B2

公开(公告)日：2020-08-04

申请号：US16229820

申请日：2018-12-21

Applicant: Huawei Technologies Co., Ltd.

Inventor： Amir Bennatan ,  Yoni Choukroun ,  Pavel Kisilev ,  Junqiang Shen

IPC: H03M13/00 ,  H04L1/00 ,  H03M13/11 ,  G06N3/08 ,  G06N3/04

Abstract: A system for reducing analog noise in a noisy channel, comprising: an interface configured to receive analog channel output comprising a stream of noisy binary codewords of a linear code; and a computation component configured to perform the following: for each analog segment of the analog channel output of block length: calculating an absolute value representation and a sign representation of a respective analog segment, calculating a multiplication of a binary representation of the sign representation with a parity matrix of the linear code, inputting the absolute value representation and the outcome of the multiplication into a neural network for acquiring a neural network output, and estimating a binary codeword by component-wise multiplication of the neural network output and the sign representation.