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公开(公告)号:US20170308324A1
公开(公告)日:2017-10-26
申请号:US15137543
申请日:2016-04-25
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor: Vanessa COURVILLE , Manuel SALDANA , Barnaby DALTON
CPC classification number: G06F3/0656 , G06F3/0608 , G06F3/0673 , G06N3/0454 , G06N3/084
Abstract: A circuit for a multistage sequential data process includes a plurality of memory units. Each memory unit is associated with a stage of the sequential data process which, for each data set inputted to the stage, the stage provides an intermediate data set for storage in the associated memory unit for use in at least one subsequent stage of the sequential data process, where each of the plurality of memory units is sized based on relative locations of the stage providing the intermediate data set and the at least one subsequent stage in the sequential data process.
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2.
公开(公告)号:US20240070221A1
公开(公告)日:2024-02-29
申请号:US18502506
申请日:2023-11-06
Applicant: Huawei Technologies Co., Ltd.
Inventor: Eyyüb Hachmie SARI , Vanessa COURVILLE , Mohan LIU , Vahid PARTOVI NIA
CPC classification number: G06F17/12 , G06F7/50 , G06F7/523 , G06F7/5443
Abstract: Methods and systems for generating an integer neural network are described. The method includes receiving an input vector comprising a plurality of input values. The plurality of input values are represented using a desired number bits. The input vector is multiplied by a weight vector, and the products of which are summed to obtain a first value. The first value is quantized and applied to a piecewise linear activation function to obtain a second value. The piecewise linear activation function is a set of linear function that collectively approximate a nonlinear activation function. The second value is quantized to generate the output of the neuron in the integer neural network.
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