公开(公告)号：US20220236909A1

公开(公告)日：2022-07-28

申请号：US17722890

申请日：2022-04-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xingcheng Hua ,  Zhong Zeng ,  Leibin Ni

IPC: G06F3/06 ,  G06N3/063

Abstract: A neural network computing chip and a neural network computing method are provided. The computing chip includes a translation circuit and a computing circuit. After input data is processed by the translation circuit, a value of each element of the data input into the computing circuit is not a negative number, thereby meeting a value limitation condition imposed by the computing circuit on the input data. Therefore, a calculation result can be obtained by performing calculation for only one time, and there is no need to perform calculation for two times. Therefore, neural network computing efficiency is improved, and a delay of a neural network operation is reduced.

公开(公告)号：US20210326687A1

公开(公告)日：2021-10-21

申请号：US17360459

申请日：2021-06-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zhe Liu ,  Zhong Zeng ,  Tieying Wang ,  Xiaoxiang Duan ,  Huimin Zhang

IPC: G06N3/063

Abstract: A neural network system includes P computing units configured to perform an operation of a first neural network layer and Q computing units configured to perform an operation of a second neural network layer. The P computing units are configured to perform computing on first input data based on N configured first weights to obtain first output data after receiving the first input data. The Q computing units are configured to perform computing on second input data based on M configured second weights to obtain second output data after receiving the second input data. The second input data includes the first output data. A ratio of N to M corresponds to a ratio of a data volume of the first output data to a data volume of the second output data.

公开(公告)号：US11853594B2

公开(公告)日：2023-12-26

申请号：US17722890

申请日：2022-04-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xingcheng Hua ,  Zhong Zeng ,  Leibin Ni

IPC: G06F3/06 ,  G06N3/063

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06N3/063

Abstract: A neural network computing chip includes a translation circuit and a computing circuit. After input data is processed by the translation circuit, a value of each element of the data input into the computing circuit is not a negative number, thereby meeting a value limitation condition imposed by the computing circuit on the input data.