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    Neural Network Computing Chip and Computing Method
    2.
    发明申请
    Neural Network Computing Chip and Computing Method 有权

    公开(公告)号：US20220236909A1

    公开(公告)日：2022-07-28

    申请号：US17722890

    申请日：2022-04-18

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Xingcheng Hua ,  Zhong Zeng ,  Leibin Ni

    IPC: G06F3/06 ,  G06N3/063

    Abstract: A neural network computing chip and a neural network computing method are provided. The computing chip includes a translation circuit and a computing circuit. After input data is processed by the translation circuit, a value of each element of the data input into the computing circuit is not a negative number, thereby meeting a value limitation condition imposed by the computing circuit on the input data. Therefore, a calculation result can be obtained by performing calculation for only one time, and there is no need to perform calculation for two times. Therefore, neural network computing efficiency is improved, and a delay of a neural network operation is reduced.

    Image recognition accelerator, terminal device, and image recognition method
    4.
    发明授权
    Image recognition accelerator, terminal device, and image recognition method 有权

    公开(公告)号：US10346701B2

    公开(公告)日：2019-07-09

    申请号：US15695681

    申请日：2017-09-05

    Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  NANYANG TECHNOLOGICAL UNIVERSITY

    Inventor： Hao Yu ,  Yuhao Wang ,  Leibin Ni ,  Wei Yang ,  Junfeng Zhao ,  Shihai Xiao

    IPC: G06K9/00 ,  G06K9/62

    Abstract: An image recognition accelerator, a terminal device, and an image recognition method are provided. The image recognition accelerator includes a dimensionality-reduction processing module, an NVM, and an image matching module. The dimensionality-reduction processing module first reduces a dimensionality of first image data. The NVM writes, into a first storage area of the NVM according to a specified first current I, ω low-order bits of each numeric value of the first image data on which dimensionality reduction has been performed, and writes, into a second storage area of the NVM according to a specified second current, (N−ω) high-order bits of each numeric value of the first image data on which dimensionality reduction has been performed. The image matching module determines whether an image library stored in the NVM includes image data matching the first image data on which dimensionality reduction has been performed.

    IMAGE RECOGNITION ACCELERATOR, TERMINAL DEVICE, AND IMAGE RECOGNITION METHOD
    5.
    发明申请
    IMAGE RECOGNITION ACCELERATOR, TERMINAL DEVICE, AND IMAGE RECOGNITION METHOD 审中-公开

    公开(公告)号：US20180012095A1

    公开(公告)日：2018-01-11

    申请号：US15695681

    申请日：2017-09-05

    Applicant: HUAWEI TECHNOLOGIES CO.,LTD. ,  NANYANG TECHNOLOGICAL UNIVERSITY

    Inventor： Hao Yu ,  Yuhao Wang ,  Leibin Ni ,  Wei Yang ,  Junfeng Zhao ,  Shihai Xiao

    IPC: G06K9/00 ,  G06K9/62

    CPC classification number: G06K9/00973 ,  G06K9/00 ,  G06K9/6201

    Abstract: An image recognition accelerator, a terminal device, and an image recognition method are provided. The image recognition accelerator includes a dimensionality-reduction processing module, an NVM, and an image matching module. The dimensionality-reduction processing module first reduces a dimensionality of first image data. The NVM writes, into a first storage area of the NVM according to a specified first current I, ω low-order bits of each numeric value of the first image data on which dimensionality reduction has been performed, and writes, into a second storage area of the NVM according to a specified second current, (N−ω) high-order bits of each numeric value of the first image data on which dimensionality reduction has been performed. The image matching module determines whether an image library stored in the NVM includes image data matching the first image data on which dimensionality reduction has been performed.

    Storage and Computing Unit and Chip
    7.
    发明申请
    Storage and Computing Unit and Chip 有权

    公开(公告)号：US20220262435A1

    公开(公告)日：2022-08-18

    申请号：US17733233

    申请日：2022-04-29

    Applicant: Huawei Technologies Co., Ltd.

    Inventor： Jianxing Liao ,  Wei Wu ,  Leibin Ni ,  Kanwen Wang ,  Rui Zhang

    IPC: G11C13/00

    Abstract: This application provides a unit, including a first transistor, a memristor, and a resistance modulation unit, where a first port of the resistance modulation unit and a first port of the memristor are connected to a first electrode of the first transistor, and the first electrode of the first transistor is configured to control the first transistor to be connected and disconnected; the resistance modulation unit is configured to adjust, based on a resistance of the memristor, a voltage applied to the first electrode of the first transistor; where the resistance of the memristor is used to indicate the first data stored by the memristor; and when a voltage used to indicate second data is input to a second electrode of the first transistor which is configured to output a computation result of the first data and the second data from a third electrode of the first transistor.

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