公开(公告)号：US20210182200A1

公开(公告)日：2021-06-17

申请号：US16933357

申请日：2020-07-20

Applicant: Huazhong University of Science and Technology

Inventor： Xiaofei LIAO ,  Yu HUANG ,  Long ZHENG ,  Hai JIN

IPC: G06F12/0862

Abstract: The present invention relates to a graph-computing-oriented heterogeneous in-memory computing apparatus, comprising a memory control unit, a digital signal processing unit, and a plurality of analog signal processing units using the memory control unit.

公开(公告)号：US20240330369A1

公开(公告)日：2024-10-03

申请号：US18610495

申请日：2024-03-20

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY ,  ZHEJIANG LAB

Inventor： Long ZHENG ,  Haiheng HE ,  Xiaofei LIAO ,  Hai JIN ,  Dan CHEN ,  Yu HUANG

IPC: G06F16/901 ,  G06F40/30

CPC classification number: G06F16/9024 ,  G06F40/30

Abstract: A method for incremental metapath storage and dynamic maintenance is provided, which includes, reformatting metapath instances, from a designated heterogeneous graph and of a designated metapath type, into path graphs; executing graph updating tasks and performing dynamic maintenance on the updated path graphs, traversing the path graph to obtain the location of metapath updates and update the path graph; for metapaths with length greater than 2 and with symmetrical central portion, central merge operation is performed to simplify path graph and perform subsequent restoration operation; and directly perform restoration operation on path graphs that do not meet the merging conditions. The present disclosure utilizes characteristics of graph update to obtain locality of metapath updates, and combines internal relationship characteristics of metapath instances to greatly speed up metapath generation and achieve real-time inference of dynamic heterogeneous graph models.

公开(公告)号：US20240220541A1

公开(公告)日：2024-07-04

申请号：US18497233

申请日：2023-10-30

Applicant: Huazhong University of Science and Technology ,  Zhejiang Lab

Inventor： Long ZHENG ,  Chaoqiang LIU ,  Xiaofei LIAO ,  Hai JIN ,  Yu HUANG ,  Zhaozeng AN

IPC: G06F16/901

CPC classification number: G06F16/9024

Abstract: An FPGA-based method and system for accelerating graph construction is provided, the method including: sampling neighborhood of each vertex in stored data and recording a traversal order of the vertices; according to the vertex traversal order, grouping the vertices into blocks and processing them by block-granularity, so as to at least obtain distance values between each two sampled neighbors of vertices in each block; according to the said distance values, updating neighborhoods of the two relevant vertices; and processing all of the blocks, starting a new iteration, until a satisfying precision or a predetermined limit of the number of iterations has been reached. The present disclosure utilizes the advantages of FPGA platform including flexibility, low power consumption and high parallelism, combined with the characteristics of graph construction algorithm, thereby greatly improving construction speed and reducing processing power consumption, so as to enable large-scale graph construction task processing in the datacenter.