公开(公告)号：US20250139005A1

公开(公告)日：2025-05-01

申请号：US18893397

申请日：2024-09-23

Applicant: Huazhong University of Science and Technology ,  ZHEJIANG LAB

Inventor： Zhiyuan SHAO ,  Sitong LU ,  Xiaofei LIAO ,  Hai JIN

IPC: G06F12/0802

Abstract: A cache-designing method using cache lines to record cache-miss information is provided, wherein cache lines and cache-miss information are stored in a common storage space by means of shared storage. Tags of cache lines, as well as cache lines and cache-miss information, are stored separately in different static random-access memories, wherein multiple independent memories are used for tags, while a single memory is for cache lines and cache-miss information. A request-processing pipeline and a response-processing pipeline are constructed to be parallelable and used respectively for processing memory-access requests and for processing memory-response data. As compared to existing non-blocking cache designs that support plenty of miss status holding registers, the present disclosure allows storage sharing between cache data and cache-miss information, and leverages dual-port feature of static random-access memories in FPGA, so as to design separate pipelines to achieve memory access respectively for memory-access request processing and for memory-response data processing.

公开(公告)号：US20240330369A1

公开(公告)日：2024-10-03

申请号：US18610495

申请日：2024-03-20

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY ,  ZHEJIANG LAB

Inventor： Long ZHENG ,  Haiheng HE ,  Xiaofei LIAO ,  Hai JIN ,  Dan CHEN ,  Yu HUANG

IPC: G06F16/901 ,  G06F40/30

CPC classification number: G06F16/9024 ,  G06F40/30

Abstract: A method for incremental metapath storage and dynamic maintenance is provided, which includes, reformatting metapath instances, from a designated heterogeneous graph and of a designated metapath type, into path graphs; executing graph updating tasks and performing dynamic maintenance on the updated path graphs, traversing the path graph to obtain the location of metapath updates and update the path graph; for metapaths with length greater than 2 and with symmetrical central portion, central merge operation is performed to simplify path graph and perform subsequent restoration operation; and directly perform restoration operation on path graphs that do not meet the merging conditions. The present disclosure utilizes characteristics of graph update to obtain locality of metapath updates, and combines internal relationship characteristics of metapath instances to greatly speed up metapath generation and achieve real-time inference of dynamic heterogeneous graph models.

公开(公告)号：US20240061779A1

公开(公告)日：2024-02-22

申请号：US18145565

申请日：2022-12-22

Applicant: Huazhong University Of Science And Technology ,  Zhejiang Lab

Inventor： Long ZHENG ,  Qinggang WANG ,  Xiaofei LIAO ,  Ao HU ,  Hai JIN

IPC: G06F12/0806 ,  G06F12/10

CPC classification number: G06F12/0806 ,  G06F12/10 ,  G06F2212/1016

Abstract: The present invention relates to a hardware accelerator for hypergraph processing and its operating method, the hardware accelerator comprising: a data loader: for, in the presence of a data-centric load-trigger-reduce execution model, reading hypergraph partition data from an off-chip memory successively according to hypergraph data structure and an order of hypergraph partitions; an address translator, for deploying the hypergraph data into a private register of a processor and/or into a buffer memory according to a priority level of loaded data, and recording corresponding offset information; a task trigger, for generating computing tasks according to the loaded data, and scheduling the computing tasks into the processor; the processor, for receiving and executing the computing tasks; a reducer, for scheduling intermediate results into a first-priority-data reducer unit or a second-priority-data reducer unit depending on the priority level of the data so as to execute a reducing operation for the intermediate results. In view of the shortcomings of task-centric hardware accelerators, the present invention can prevent any possible data conflict during parallel execution of multiple processing units.

公开(公告)号：US20240053892A1

公开(公告)日：2024-02-15

申请号：US18145552

申请日：2022-12-22

Applicant: Huazhong University Of Science And Technology ,  Zhejiang Lab

Inventor： Long ZHENG ,  Qinggang WANG ,  Xiaofei LIAO ,  Zhaozeng AN ,  Hai JIN

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0673 ,  G06F3/0656

Abstract: The present invention relates to a dynamic memory management apparatus and method for HLS, the apparatus at least comprising: several searching and caching modules and several modifying and writing-back modules, wherein the searching and caching modules are in connection with a DRAM storing module and a BRAM buffer, respectively, and the modifying and writing-back modules are in connection with the DRAM storing module and the BRAM buffer, respectively, wherein the BRAM buffer is for caching information about nodes on a search path and registering information about modification made to the nodes; the searching and caching module is for reading node data from the DRAM storing module according to received operators and node addresses, and writing the node data into the BRAM buffer; and the modifying and writing-back module reads the node data from the BRAM buffer and writes the node data back into the DRAM storing module. Aiming at the defect that the traditional operating system is directly transplanted to the FPGA and has low execution efficiency, the present invention utilizes the advantage of the large capacity of the DRAM on the FPGA to realize efficient dynamic memory allocation and deallocation, and improve the usability and code reusability of HLS.

公开(公告)号：US20240220541A1

公开(公告)日：2024-07-04

申请号：US18497233

申请日：2023-10-30

Applicant: Huazhong University of Science and Technology ,  Zhejiang Lab

Inventor： Long ZHENG ,  Chaoqiang LIU ,  Xiaofei LIAO ,  Hai JIN ,  Yu HUANG ,  Zhaozeng AN

IPC: G06F16/901

CPC classification number: G06F16/9024

Abstract: An FPGA-based method and system for accelerating graph construction is provided, the method including: sampling neighborhood of each vertex in stored data and recording a traversal order of the vertices; according to the vertex traversal order, grouping the vertices into blocks and processing them by block-granularity, so as to at least obtain distance values between each two sampled neighbors of vertices in each block; according to the said distance values, updating neighborhoods of the two relevant vertices; and processing all of the blocks, starting a new iteration, until a satisfying precision or a predetermined limit of the number of iterations has been reached. The present disclosure utilizes the advantages of FPGA platform including flexibility, low power consumption and high parallelism, combined with the characteristics of graph construction algorithm, thereby greatly improving construction speed and reducing processing power consumption, so as to enable large-scale graph construction task processing in the datacenter.

公开(公告)号：US20240364502A1

公开(公告)日：2024-10-31

申请号：US18631621

申请日：2024-04-10

Applicant: Huazhong University of Science and Technology

Inventor： Peng XU ,  Mengyang YU ,  Wei WANG ,  Yixin SU ,  Yubo ZHENG ,  Hai JIN

IPC: H04L9/08 ,  H04L9/32

CPC classification number: H04L9/0819 ,  H04L9/0869 ,  H04L9/3236

Abstract: A method and system for encryption and assured deletion of information is provided, the method at least includes: sorting fields of the information into at least two sensitivity levels by sensitivity; generating encryption keys and key shards thereof based on predetermined thresholds, and creating mapping between targets and the key shards, based on the encryption keys for the sensitivity levels, encrypting the information fields of the corresponding sensitivity levels and deleting the original information and encryption keys; and in response to reception of a recover request, recovering the encryption keys based on the key shards and performing decryption, so as to recover the original information. The present disclosure aims at the problem that information is difficult to be safely stored and assuredly deleted, and realizes multi-party security key deletion of encrypted personal information.

公开(公告)号：US20240362187A1

公开(公告)日：2024-10-31

申请号：US18631660

申请日：2024-04-10

Applicant: Huazhong University of Science and Technology

Inventor： Peng XU ,  Shuning XU ,  Wei WANG ,  Runze XU ,  Tingting RAO ,  Hai JIN

IPC: G06F16/16 ,  G06F21/60

CPC classification number: G06F16/162 ,  G06F21/60 ,  G06F2221/2143

Abstract: A method and system for overwriting-based deletion of information and verification of deletion is provided, wherein the method at least includes: receiving a deletion request and/or a random seed; performing fine-grained overwriting on the information by means of random overwriting; in response to an extraction request for a post-deletion state, making a master node in a source domain of the information broadcast the extraction request to at least one slave node; and sending the post-deletion state fed back by the slave node and a related state-verification parameter to a verifying terminal, so that the verifying terminal verifies an overwriting result based on a verifiable pseudo-random function. Thus, the present application can effectively prevent information recovery after being logically deleted, and efficaciously ensure verifiability as well as non-recoverability of deleted information, thereby assuring non-recoverable deletion and providing verifiability of deletion to information subjects.

公开(公告)号：US20240192929A1

公开(公告)日：2024-06-13

申请号：US18475447

申请日：2023-09-27

Applicant: Huazhong University of Science and Technology

Inventor： Zhen LI ,  Ruqian ZHANG ,  Deqing ZOU ,  Hai JIN ,  Yangrui LI

IPC: G06F8/35 ,  G06F8/41

CPC classification number: G06F8/35 ,  G06F8/42

Abstract: A sample-difference-based method and system for interpreting a deep-learning model for code classification is provided, wherein the method includes a step of off-line training an interpreter: constructing code transformation for every code sample in a training set to generate difference samples; generating difference samples respectively through feature deletion and code snippets extraction and then calculating feature importance scores accordingly; and inputting the original code samples, the difference samples and the feature importance scores into a neural network to get a trained interpreter; and a step of on-line interpreting the code samples: using the trained interpreter to extract important features from the snippets, then using an influence-function-based method to identify training samples that are most contributive to prediction, comparing the obtained important features and the most contributive training samples, and generating interpretation results for the object samples. The inventive system includes an off-line training module and an on-line interpretation module.

公开(公告)号：US20220255739A1

公开(公告)日：2022-08-11

申请号：US17444224

申请日：2021-08-02

Applicant: Huazhong University of Science and Technology

Inventor： Peng XU ,  Tianyang CHEN ,  Yubo ZHENG ,  Hai JIN ,  Wei WANG

IPC: H04L9/30 ,  H04L9/06

Abstract: The present invention relates a method for ensuring search completeness of searchable public key encryption, applicable to a blockchain network formed by a plurality of computer nodes. The method at least comprises: the blockchain network receiving a keyword ciphertext and a corresponding file-identifier ciphertext generated by a transmitting end based on the public key encryption, and at least one miner storing the ciphertexts in a ciphertext table; the blockchain network receiving a search trapdoor Tw transmitted by a receiving end, generated according to a private key and a keyword w to be searched; the at least one miner in the blockchain network performing a secure search based on information of a state table and the search trapdoor Tw, and outputting a search result to the blockchain network; and the blockchain network feeding the search result back to the receiving end. The invention uses the blockchain technology to solve the long-standing search completeness problem in searchable public key encryption, and the proposed method has universality.

公开(公告)号：US20210250299A1

公开(公告)日：2021-08-12

申请号：US17248519

申请日：2021-01-28

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Fangming LIU ,  Hai JIN ,  Miao LI

IPC: H04L12/851 ,  H04L12/803 ,  G06F16/22 ,  H04L12/24

Abstract: The present invention relates to a container-based network function virtualization (NFV) platform, comprising at least one master node and at least one slave node, the master node is configured to, based on interference awareness, assign container-based network functions (NFs) in a master-slave-model-based, distributed computing system that has at least two slave nodes to each said slave node in a manner that relations among characteristics of the to-be-assigned NFs, info of load flows of the to-be-assigned NFs, communication overheads between the individual slave nodes, processing performance inside individual slave nodes, and load statuses inside individual said slave nodes are measured.